Fmax

[Altera_Forum]

Hi Everyone, 

  My system is built around a Cyclone part and includes a video generation block. Because of this I can&#39;t compromise on my Fmax of 65MHz - it is the video clock frequency. As the system has grown (to about 90% of the logic cells used) it has become increasingly difficult to reach Fmax.  I have been through all the suggestions that the Timing Optimisation Advisor has to offer. Basically, I now just keep adjusting the Fitter seed and re-compiling until Fmax is met. This can take days as each compile takes about an hour.  Sometimes it fails to reach Fmax but only misses by a couple of percent. My questions are: How accurate is the Fmax calculation? Is it overly-pessimistic about the real hardware? Must the Fmax rule be obeyed absolutely? Is there an acceptable tolerance when Fmax isn&#39;t met.  Thanks for any advice or help.  Banx.  http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

You may try quartus&#39;s design space explore. It can search for the best Fmax. It always take a long time. 

 You should try to reduce your logic. Try both F core and S core. Reduce cache usage.

[Altera_Forum]

Thanks Hippo. Some good pointers, I&#39;ll certainly investigate the space explorer. 

 I&#39;d still like to hear other developers views about how strictly we need to keep within Fmax. I know it amounts to &#39;over-clocking&#39; and should be avoided but if I get to within 1% of Fmax it could save me maybe two days of re-compiling. I&#39;ve never issued a build to a customer that didn&#39;t meet Fmax but I am now developing s/w on a board that only achieved 64.1MHz (target 65MHz). I&#39;ll play with it for a week or so and let you all know if I get any odd happenings.  I should have mentioned earlier that I&#39;m stuck with my particular Cyclone part, EP1C12 as parts with more logic cells have a different footprint. Also I&#39;m using speed grade 7.  Thanks All.  Banx.

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  within 1% of Fmax it could save me maybe two days of re-compiling.[/b]  --- Quote End ---   Are you sure? On slow PC - Celeron 900MHz(typical 950, but decreased for lower power) and 384Mb RAM, system for slowest CycloneII 2C8F256-8 fitted within 30 min.  Enable in quartus fitter settings most physical resynthesis options, such as  comb. logic and register retiming. Set effort to extra. Set router optimisation level to maximum and placement effort to 3.0. This settings can help increase fmax up to 15%.  On 2C8F256-8 NiosII/s without multipler can work up to 85MHz, and with multipler up to 75 MHz(timings based on timing analyser).  Find in timing analyser critical path. If critical path outside NiosII core, then place slow device on separate clock domain.  Quartus can work faster with more system memory. PC must have more than 1 Gb RAM, 512 Mb for windows xp and other for quartus.

[Altera_Forum]

--- Quote Start ---  originally posted by banx@Jul 10 2006, 01:24 PM thanks hippo. some good pointers, i&#39;ll certainly investigate the space explorer.  i&#39;d still like to hear other developers views about how strictly we need to keep within fmax. i know it amounts to &#39;over-clocking&#39; and should be avoided but if i get to within 1% of fmax it could save me maybe two days of re-compiling. i&#39;ve never issued a build to a customer that didn&#39;t meet fmax but i am now developing s/w on a board that only achieved 64.1mhz (target 65mhz). i&#39;ll play with it for a week or so and let you all know if i get any odd happenings.  i should have mentioned earlier that i&#39;m stuck with my particular cyclone part, ep1c12 as parts with more logic cells have a different footprint. also i&#39;m using speed grade 7.  thanks all.  banx. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=16767)  --- quote end ---    --- Quote End ---    Quartus reports Fmax based upon statistical data. It is worst case for that die at worst case temperature. When the parts are produced they are binned for the speed grade. You are not in the fastest speed grade part. A potential solution for you would be to go to the -6 speed grade part, but it will be more expensive. As the process yields improve they will sell -6 speed grade parts as -7s because the part is guaranteed to run faster.   You can try to improve your Fmax by changing the seed number. But DSE will give you the best results, by telling you what synthesis options will give you best results.   The most appropriate fix for your design is to find out what paths are having trouble meeting timing and fixing those paths. There are a lot of ways to correct for not meeting timing (reregistering, multi-cycle, etc.).   Your reference to overclocking isn&#39;t accurate.   Do not ship parts that don&#39;t meet timing. The parts may not work when they get hot and/or a certain lot of parts produced will not work or behave erraticaly. I have heard however that there is some statistical confidence if you are within say 1% of Fmax. Perhaps an Altera FAE can help you further.