ddr_sdram problem

[Altera_Forum]

i use the ddr_sdram for a system,but when i compile the system,errors happened in the fitter step.the errors are: 

  Error: Specified DDIO registers are not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output _cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin|ddio_out_sbf:auto_generated|output _cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit  Error: Register "std_2C35:inst|sdram:the_sdram|sdram_auk_ddr_sdram:sdram_auk_ddr_sdram_inst| sdram_auk_ddr_datapath:ddr_io|sdram_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit   why??

[Altera_Forum]

I've had the same problem, was there any solution to this?

[Altera_Forum]

Not that I'm an expert when it comes to DDR but did you assign the DDR I/O to the correct banks? (not all I/O on the FPGA can drive DDR SSTL2 signals) If you are not aware of that you might want to take a look at a Nios II Cyclone II or Stratix II RoHS example design. Open the DDR and notice that only two banks of I/O are being use for the DDR signals. 

 Now if those errors are coming from an example design (std_2C35 suggests that it is) have you regenerated the system in SOPC Builder? The DDR IP uses paths to find the logic making up the controller so it could be that your logic isn't being pulled in correctly.  I hope one of those ideas helps. If not please indicate whether or not you are running a custom design or an example design provided in the kit.

[Altera_Forum]

I've instantiated the design fromSOPC builder for the Cyclone II board. As far as I can see I've implemented exactly the same banks and everything else as in the example design. Apologies, I missed that the top message was using the standard example design, I'm using the same board but a new project. 

 By removing the offending commands I was able to synthesis the design, so it doesn't really matter any more. But I assume that these instructions are included for a reason? I would like to not have to hack these out of the assignment file if I could.