DDR SDRAM vs SSRAM

Altera_Forum · ‎08-15-2006

I've develop a project with 3 Nios II processors and 4 on-chip memories and mutexes. And I'm using a Development kit Cyclone II and Quartus and Nios IDE 5.0. Often in my code the processors need to verify the state of one or two variables in the shared on-chip memories. For example:

....

while(shared_memory->flag =! OK); (***)

lock_mutex;

read_and_write_data;

unlock_mutex;

....

So, the problem is that: The application only runs well if I store code (.text,.rodata,.rwdata,.heap,.stack) of the the processors in the DDR SDRAM and if I use standard processors. If I use fast processors or if I try to store code of two of these processors in the SSRAM, the application is paused in almost all the points where this kind of verifying (***) is made.

No problems are displayed in Nios terminal when downloading codes. What is stranger is that data among processors are in fact sent and received by the others however it seems the processors are not being able to recognize that the state of a flag in a shared memory has been changed.

I've just noticed that, when cpus paused, if I use the "step over" tool (in nios IDE debug perpective), sometimes, this condition (***) is successful verified and the execution go a head until another verification is necessary. I've just try also lock a mutex before make these verications but the problem remains.

I can't understand that. Can't I store code in SSRAM? Why using nios/f processors provides me this problem?

My goal using SSRAM and Nios /f is to reduce conflict among processors in access to code in just one memory device.

Thanks a lot.

mendonca.

Altera_Forum · ‎08-17-2006

Hi mendonca,

just a guess: the nios/f has data cache.

If another avalon master changes the value of your flag in memory, the nios/f processor doesn't notice, because it loads the value from the cache. If you load the values by using the 'ldwio' opcode, you read the value directly from memory.

And depending on your optimization level, the value isn't read at all from memory, only a value in a processor register is checked. You can cirumvent this by adding 'volatile' to your variable declaration.

Also, isn't there a hardware mutex component that synchorinzes access to memory between different processors?

Wolfgang

Altera_Forum · ‎08-17-2006

while(shared_memory->flag =! OK); (***)

mendonca,

are you shure:

You want to load 'shared_memory->flag' with the inverted value of 'OK' and then check if this is not zero? Or do you want to wait until the flag is '!OK'?

If so you have to write:

while(shared_memory->flag != OK);

Mike

Altera_Forum · ‎08-17-2006

Sorry for the mistake, Mike. I've just typed wrong. (There is no gcc compiler in Nios Forum Post System, hehehe!) The correct sentence is, in fact:

while(shared_memory->flag != OK);

Altera_Forum · ‎08-17-2006

Hi, Wolfang.

--- Quote Start ---

originally posted by wpaulus@Aug 17 2006, 07:03 AM

just a guess: the nios/f has data cache.

if another avalon master changes the value of your flag in memory, the nios/f processor doesn't notice, because it loads the value from the cache.

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--- quote end ---

--- Quote End ---

Good point! I've thought that declaring my on-chip memories instances as volatile, this problem couldn't happen. However, the problem is still deeper. I had already also tried to run the application under Nios/f processor without data cache (0Kb). The problem remained.

--- Quote Start ---

originally posted by wpaulus@Aug 17 2006, 07:03 AM

if you load the values by using the 'ldwio' opcode, you read the value directly from memory.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17667)

--- quote end ---

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I've enjoyed your suggestion too much. Can you send me a simple example of how can I use that opcode. I don't know it yet. Or, maybe, the name of the header file where are declaring the routines I need to use. With this I suppose I can take more informations in Nios II Software Handbook.

--- Quote Start ---

originally posted by wpaulus@Aug 17 2006, 07:03 AM

and depending on your optimization level, the value isn't read at all from memory, only a value in a processor register is checked. you can cirumvent this by adding 'volatile' to your variable declaration.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17667)

--- quote end ---

--- Quote End ---

I've checked my code again and, in fact, I used 'volatile' in all the declaration of the 4 shared memories.

--- Quote Start ---

originally posted by wpaulus@Aug 17 2006, 07:03 AM

also, isn't there a hardware mutex component that synchorinzes access to memory between different processors?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=17667)

--- quote end ---

--- Quote End ---

Yes. Actually, each memory has a mutex protecting it.

This question remembers me another doubt. What, in fact, happens when a processor try to verify the value of a variable, like in (***)? I've noticed, at least in my projects, that checking this before or after lock a mutex makes no difference. Is there no conflit among processor when trying to verify memory on this way?

Thank you to much, Wolfang. We had a good discussion here.

I'll be waiting new suggestions from Nios Community.

Regards,

Mendonça.

Altera_Forum · ‎08-18-2006

Hi mendonca,

--- Quote Start ---

originally posted by mendonca@Aug 17 2006, 08:56 AM

i've enjoyed your suggestion too much. can you send me a simple example of how can i use that opcode. i don't know it yet. or, maybe, the name of the header file where are declaring the routines i need to use. with this i suppose i can take more informations in nios ii software handbook.

--- Quote End ---

In the Nios II Software Developer's Handbook look at Chapter 7 Cache & Tightly-Coupled Memory. There is a section about Managing Cache in Multi-Master Systems. Cache bypassing is explained there.

Just another heretic thought: Have you connected your on-chip memory to all of your processors in sopc builder? If they aren't connected and you read from the address you get undefined results, maybe 0x00 or 0xff.

while(shared_memory->flag != OK); (***)
lock_mutex;
read_and_write_data;
unlock_mutex;

btw, why do you check the flag before taking the (hardware) semaphore? The purpose of the semaphore is to synchronize access to shared memory. Why not use the api provided by Altera for the semaphore and leave the work to their code?

Regards,

Wolfgang