WM8731 on the Altera DE2

[Altera_Forum]

Even tho it's not related to the Nios II at all, i'm posting here since the terasIC forum is still down. 

 I've been struggling to get valid data out of the WM8731 (Audio Codec) ADC for 3 days with no results.  Hypothesis: A null linein should generate zeros at the AUD_ADCDAT output. Or if there are some ones, they should be noise (at LSBs positions). This is not my case, i get some MSBs set to 1. With a 24bits output, i always get the first 13 MSBs as ones. To give you an idea, most of the time a get the following pattern (both left and right channels) or a subtle different one (some LSBs may vary): 0b111111111111101011001000.  Testing parameters: - Master mode (MS=1) - XTI/MCLK of 12.5MHz (specs says i should feed a 12.288MHz clock, could this be the issue??). - I've tried different sample rates for the ADC (8kHz and 48kHz). Most tests were done in 48kHz (BOSR=0, SR[3..0]=0000). - Normal mode (not USB mode) - LINMUTE is disabled for both linein - INSEL=0 (line in select) - Tried all formats. Most tests were done with i2s - Tried all IWL, most tests were done with 24bits  I've also tried the DE2_i2sound (i just outputed AUD_ADCDAT to a GPIO_0 to see the output) demonstration, I get the same output when there's no signal at linein nor micin...  Has anybody been able to get proper data from the ADC? I welcome any clue or tips.  thanks,  -Pascal

[Altera_Forum]

Did my question fell thru the cracks of friday PM? 

Or perhaps no one tried to use the ADC on the WM8731?  -Pascal

[Altera_Forum]

I've just tried using a MCLK of 18.432MHz (actuel 18.421053MHz) generated with a PLL. 

Nothing changed, ADC still gives me non-zeros in MSBs when there's no linein at all.  -Pascal PS: I haven't forgotten to update the value of BOSR.

[Altera_Forum]

FWIW, i've done more experiments. 

Still get too much noise on the ADC therefore i believe i get invalid data.  I've tried running it in slave mode. I've tried USB mode (12MHz MCLK).