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Debugging CPU failure

Altera_Forum
Honored Contributor II
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Hello all, 

 

I run a Nios II/f processor on a Stratix II S30 device, the software working in unison with a VHDL design on the same chip. The system runs in a high-noise environment, and I have sporadic events of CPU getting suddenly stuck. I have pretty much narrowed down the problem to electrical noise, and can reliable reproduce it. I have also implemented a watchdog in the VHDL code which proved that the CPU got stuck (the software was knocked out). 

 

A couple of questions: 

 

1) What can knock a Nios running software out ? Can it be a noise induced on the system clock that causes Nios to "skip a beat" and enter an illegal state ? 

 

2) What options of debugging do I have, from the Nios side. I.e. if I want to see how exactly it is stuck. Can I somehow take out the program counter to external pins ? Or maybe some internal CPU registers that could help me identify the problem ? 

 

TIA
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Altera_Forum
Honored Contributor II
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There are a lot of possabilties that could lead to a instable system when running under "high-noise" inviroment.  

 

what exactly do you mean with high-noise ? do you mean industrial application with lots of disturbances on the power suply (meaning NOT a lab power supply) with variation of voltage and peaks, dropouts, lot of ac ... and in addition emc signals from power converters for motion control ... 

 

from my experience there are two main points to check. 

 

1.a ) the fpga .... use only a 100% fully synchron design, no asyncron design. i have seen a stable system getting instable under temperature reason was an asynchron part.  

 

1.http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif check for over and undershots of your signals leaving / entering the fpga. if you have f.e. undershots they could lead to a "clock edge" that can trigger a flip flop as these undershots move the voltage levels. you can easily compensate most of them by tunig the pin assignments. 

 

2.) the pcb / layout ....  

 

2.a) you need a power suppply system that is stable enough with a low impedance over a wide frequency range.  

f.e. if your clock is 50MHz then you will need at least 3 times 50MHz, better 5x times, meaning 150 to 250MHz signalspeed. the 50MHz is pure sine wave. 250MHz are needed for rectangle shape. so your power supply system needs to be low impedance (less than Z=1Ohm better 0.1Ohm) for a minimum of this 250MHz. a wide band low impedance. 

 

2.http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif your power system needs to be able to feed the power pins when your fpga switches the flip flops and needs current. if the power system is not stable enough the voltage could drop for a short moment under a certain needed value ... 

we calculate the minimum cap uF each components needs (current, access time, allowed voltage ripple) and the effective area this cap works. 

 

Over all if your design is not bullet proof then of course noise could lead to a "switching" flip-flop when it is not intended to switch. image what could happen ... 

 

Regards 

 

Michael Schmitt
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Altera_Forum
Honored Contributor II
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ups ... i haven&#39;t intended to write smilies ...

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Altera_Forum
Honored Contributor II
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Thanks for the tips - my design is fully synchronous, and in fact my VHDL inside that FPGA keeps working even after the Nios software is knocked out. I&#39;m still interested to know how I can analyze the failure of the Nios software (without using a debugger, which doesn&#39;t work in my environment because of the noises affecting the USB blaster).

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