2 clocks in 1 module

[Altera_Forum]

Hi, 

 My module , which is a slave , needs 2 clock inputs : system_clk (85MHz) and function_clk (27MHz)  system_clk is specified when I assign signals in signal tab of component editor (avalon_slave_0 , clk).  I already created a pll producing 27MHz inside SOPC. Now I want to specify function_clk to work at that clock (27MHz).   How can I do that ?  Thanks in advance,  Quan

[Altera_Forum]

I take it this is a single ported Avalon slave component. So you want 85MHz to be specified in SOPC Builder and be able to drive a secondary 27MHz clock into your component. The easiest way to do this is to export the 27MHz clock in component editor so it will pop up to the top of SOPC Builder. Then you would wire it with the 27MHz clock coming out of the top of SOPC Builder from the PLL. 

 **Hint** If you name your 27MHz clock in SOPC Builder the same name as what your component expects SOPC Builder will wire it up automatically for you. See this solution for more information:  http://www.altera.com/support/kdb/solution...022006_736.html (http://www.altera.com/support/kdb/solutions/rd05022006_736.html)

[Altera_Forum]

--- Quote Start ---  originally posted by badomen@Oct 3 2006, 12:54 AM i take it this is a single ported avalon slave component.  so you want 85mhz to be specified in sopc builder and be able to drive a secondary 27mhz clock into your component.  the easiest way to do this is to export the 27mhz clock in component editor  so it will pop up to the top of sopc builder.  then you would wire it with the 27mhz clock coming out of the top of sopc builder from the pll.  **hint**  if you name your 27mhz clock in sopc builder the same name as what your component expects sopc builder will wire it up automatically for you.  see this solution for more information:  http://www.altera.com/support/kdb/solution...022006_736.html (http://www.altera.com/support/kdb/solutions/rd05022006_736.html) <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18519)  --- quote end ---    --- Quote End ---    Hi BadOmen,  After creating clk27 , I do either of the following :   1) I made a wire connecting clk27 and function_clk (I meant to feed clk27 to function_clk)  But this causes an error :   Error: Can&#39;t fit fan-out of node std_2C35:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk2 into a single clock region  2) I rename clk27 to function_clk as you suggested , i hope it could automatically wire it to function_clk in my module.   There is no error occurring for this way.  But when I test the function_clk of my module using SignalTAP , it doesn&#39;t oscillate (always 0)  What is the problem ?  Regards,  Quan

[Altera_Forum]

By the way , I&#39;d like to ask you how I can make this module work in ModelSIM. 

 system_clk (85MHz) is ok but ModelSIM doesn&#39;t understand my function_clk which was specified as an export in SOPC Builder, 27MHz-expected ( it is always Z in ModelSIM)  Thanks in advance,  Quan

[Altera_Forum]

Hi guys, 

 I got the reason why i took that error. It is because we cannot feed the output of a pll to another. To solve the issue , just use one of the original FPGA Clock Input pins which are described in manual document for each kit.  By the way , to make ModelSIM understand the 27MHz function_clk , right click on that signal in Wave window and choose "Force".  Cheer,  Quan