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50Mhz to 60Mhz

Altera_Forum
Honored Contributor II
1,372 Views

Dear everyone! 

 

I desig a nios2 system with EPC2C5Q208C8 ,DM9000A, running uClinux, 

when I test at 50Mhz, everything is OK, but when I chanhe it to 60 Mhz, the ethernet can't work! and I try to modify the interface timing specification ,Tsu, Th, ,it still can't work but kernel and other application could work correctly! 

who can tell me what shall I do ? 

and what's the maximum frequency the EPC2C5Q208C8 support? 

 

Best Regards! 

Fei Wu  

 

THANK YOU VER MUCH!
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5 Replies
Altera_Forum
Honored Contributor II
409 Views

1. if you change the system clock, you should regenerate hardware in sopc builder. 

make sure sdram and io timing are met. 

 

2. try to reduce your logic and optimze the timing. 

try both S core and F core, use smaller cache size. 

try "design space explorer" in quartus. 

I have a 2C5-8 with Fmax about 76MHz.
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Altera_Forum
Honored Contributor II
409 Views

HI Hippo, 

Thank you very much! 

I have rebuild it in SOPC builder, and SDRAM is oK because the linux kernel run correctly! 

I use LE about 94%, and S or F core all is not OK! 

I have never use the DSE, I will try to use it! 

 

Could you please give me some advice about how to do? 

 

Best Regards! 

 

Fei WU
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Altera_Forum
Honored Contributor II
409 Views

youe LE usage is quite high. It is difficult to achive high speed. 

try reduce your logic, remove features which are not critical. 

I would try to use software to replace hardware for tasks that are not timing critical. 

 

To DSE, 

quartus->tools->launch Design Space Explore 

and check "Project use Quartus II integragted synthesis" 

 

For DM9000A, can the chip be detected and configed ?
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Altera_Forum
Honored Contributor II
409 Views

the dm9000a only works with 25 MHz, if you cant generate this clock with a FPGA PLL tthen you must provide a 25 MHz cristal. 

On the De2 board the clock for the dm9000a is derived from the 50 MHz system clock.  

See the de2 brd verilog file. 

reg ENET_CLK; 

always@(posedge OSC_50) ENET_CLK=~ENET_CLK;
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Altera_Forum
Honored Contributor II
409 Views

Dear friend, 

Thank you ver much for your reply! 

I met another very strange question! 

my nios2 is 50Mhz, and I have tested the netport for a long time. 

but the net port is wrong sometimes, while the config is ok ,accessed through nios2-terminal! 

 

# ifconfig 

eth0 Link encap:Ethernet HWaddr 00:88:00:00:66:32 

inet addr:192.168.168.1 Bcast:192.168.168.255 Mask:255.255.255.0 

UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 

RX packets:14 errors:0 dropped:0 overruns:1 frame:1 

TX packets:9 errors:0 dropped:0 overruns:0 carrier:0 

collisions:0 txqueuelen:1000 

RX bytes:0 (0.0 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif TX bytes:0 (0.0 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif  

Interrupt:4 Base address:0x920 

 

lo Link encap:Local Loopback 

inet addr:127.0.0.1 Mask:255.0.0.0 

UP LOOPBACK RUNNING MTU:16436 Metric:1 

RX packets:0 errors:0 dropped:0 overruns:0 frame:0 

TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 

collisions:0 txqueuelen:0 

RX bytes:0 (0.0 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif TX bytes:0 (0.0 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif  

 

 

I think that my PC is OK, but ping is not ok! 

 

 

C:\Documents and Settings\INTERNET>ping 192.168.168.1 

 

Pinging 192.168.168.1 with 32 bytes of data: 

 

Request timed out. 

Request timed out. 

Request timed out. 

Request timed out. 

 

Ping statistics for 192.168.168.1: 

Packets: Sent = 4, Received = 0, Lost = 4 (100% loss), 

Approximate round trip times in milli-seconds: 

Minimum = 0ms, Maximum = 0ms, Average = 0ms 

 

I don&#39;t know what happend to the DM9000A? 

 

and it will be ok some time later! 

 

Thank you very much ! 

 

Best Regards!
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