More EPCS troubles

[Altera_Forum]

Hello everybody,  

 I ran into a problem trying to let my custom board run stand-alone.  I have a EPCS1 and a CFI Flash connected to my design. I would like to store mt config data and my software in the EPCS, the Flash will be used for something different.   I have set the reset addres to the EPCS controller in SOPC builder and I checked the box which says " program software project in flash memory " in the flash programmer.   as far I can tell are these the steps I should make to run my board alone am I right in this?   But when I hit the button " program flash " the only thing I get to see in the NIOS IDE is:   #! /bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.# cd D:/" here stands normally the project path "  I know this is wrong because from what I have seen in all the other posts on the forum there should be more text and a noticed that the programming has been completed of has failed.    Does anybody know what is happening here??

[Altera_Forum]

hmmz it works now. But i had to make a board description. I thougth that it was stated that this shouldn't be necessary as of version 5.1??

[Altera_Forum]

Something has to tell the programmer how your flash is partitioned... While a target board design is no longer needed, a board description is. 

 - slacker

[Altera_Forum]

well after that I had made the board description there were a few things I had to edit manually,by using a text editor, in the .ptf file. Somehow there were a few things missing but with a reference design I was able to get it working. 

 But when I try to load something in the flash, not the EPCS, I'm getting the " no CFI table found at adress 0x000000"  what I have tried is:  use the CLI with the debug function, which gives me the following result: $ nios2-flash-programmer --cable="Usb-blaster " --device=3 -base=0x0 --debug Using cable "USB-Blaster ", device 3, instance 0x00 Resetting and pausing target processor: OK No CFI table found at address 0x0000000A Original contents (after writing 0xF0 and 0xFF to address 0x0000000A):   0: FF 7F FF 7F FF 7F FF 7F  FF 7F FF 7F FF 7F FF 7F  ................  10: FF 7F FF 7F FF 7F FF 7F  FF 7F FF 7F FF 7F FF 7F  ................  20: FF 7F FF 7F FF 7F FF 7F  FF 7F FF 7F FF 7F FF 7F  ................  30: FF 7F FF 7F FF 7F FF 7F  FF 7F FF 7F FF 7F FF 7F  ................  40: FF 7F FF 7F FF 7F FF 7F  FF 7F FF 7F FF 7F FF 7F  ................ Contents after writing       0x98 to address 0x000000B4:    Same after writing       0x98 to address 0x0000005F:    Same after writing       0x98 to address 0x0000015E:   0: 98 18 98 18 98 18 98 18  98 18 98 18 98 18 98 18  ................  10: 98 18 98 18 98 18 98 18  98 18 98 18 98 18 98 18  ................  20: 98 18 98 18 98 18 98 18  98 18 98 18 98 18 98 18  ................  30: 98 18 98 18 98 18 98 18  98 18 98 18 98 18 98 18  ................  40: 98 18 98 18 98 18 98 18  98 18 98 18 98 18 98 18  ................ Contents after writing     0x0098 to address 0x0000015E:    Same after writing     0x0098 to address 0x000000B4:    Same after writing     0x0098 to address 0x000002B2:   0: 98 00 98 00 98 00 98 00  98 00 98 00 98 00 98 00  ................  10: 98 00 98 00 98 00 98 00  98 00 98 00 98 00 98 00  ................  20: 98 00 98 00 98 00 98 00  98 00 98 00 98 00 98 00  ................  30: 98 00 98 00 98 00 98 00  98 00 98 00 98 00 98 00  ................  40: 98 00 98 00 98 00 98 00  98 00 98 00 98 00 98 00  ................ Contents after writing 0x00000098 to address 0x000002B2:    Same after writing 0x00000098 to address 0x0000015E:    Same after writing 0x00000098 to address 0x0000055A:   0: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................  10: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................  20: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................  30: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................  40: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................ Ignored possible autoselect code 90-90 as no override data present in section Ignored possible autoselect code 0090-0090 as no override data present in section Ignored possible autoselect code 00000000-00000000 as no override data present in section Leaving target processor paused  Slacker you were saying in some other posts that I should compare this data with the datasheet from my flash (Spansion S29JL064H)  How do I do this? Could you please explain it to me? My quess is that I should compare the addres and the data that is written here to the flash with the address and data in the datasheet? Am i right in this?  I also tried to give the .ptf file a few extra lines with REFDES in it, as described by tommycp in the thread" flash made me crazy for several days,no cfi table"   any help is appreciated:D  hmmz seems nobody has a clue? there must be someone how knows how to solve this???

[Altera_Forum]

anyone??

[Altera_Forum]

Have you tried running the memory test application (one of the standard software "templates") on your flash device? You can step through your flash initialization to see what's actually failing. In order to do this, you'll need to start by setting a breakpoint, just prior to your CFI flash device's initialization in alt_sys_init.c (in your syslib project). 

 Additionally, my guess is that you don't have the device wired up properly. The debug output, that you're receiving, doesn't make much sense and is suspiciously repetitive. In any case, you'll be able to see what happens, in more detail, when you step through the CFI initialization.  Oh, and welcome to the wonderful world of CFI inconsistencies. :-)  Cheers,  - slacker

[Altera_Forum]

I tried the Mem_test application. But I don't have enough space on my FPGA to run it. It a Cyclone EP1C3. It is supposed to boot only the two other Fpga's on the board. Actually there is just a onchip mem (4K),epcs controller, tri state bridge,cfi-flash, jtag uart and a few leds. this takes almost 75% of the resources I have on the EP1C3. When I build the mem-test i need to have  

 /cygdrive/c/altera/kits/nios2_51/bin/nios2-gnutools/H-i686-pc-cygwin/bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region onchip_memory_0 is full (memtest_1.elf section .text). Region needs to be 77612 bytes larger.  I just don&#39;t have this kind of space left. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif   I&#39;ll check my schematics once more to see if everything I wired up is done correctly   Thanks for the help so far Slacker       --- Quote Start ---  originally posted by slacker@Oct 19 2006, 07:25 PM have you tried running the memory test application (one of the standard software "templates") on your flash device?  you can step through your flash initialization to see what&#39;s actually failing.  in order to do this, you&#39;ll need to start by setting a breakpoint, just prior to your cfi flash device&#39;s initialization in alt_sys_init.c (in your syslib project).  additionally, my guess is that you don&#39;t have the device wired up properly.  the debug output, that you&#39;re receiving, doesn&#39;t make much sense and is suspiciously repetitive.  in any case, you&#39;ll be able to see what happens, in more detail, when you step through the cfi initialization.  oh, and welcome to the wonderful world of cfi inconsistencies. :-)  cheers,  - slacker <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18801)  --- quote end ---    --- Quote End ---