S/F core

[Altera_Forum]

Dear everyone, 

My nos2 is 50Mhz, S -core, has been tested, all is ok!  when I change to 50M/F-core, select the instruction cache and data cache, the "netflash" command is not ok! then I deselect the data cache, the netflash is ok! I don't know what happened!  Could you please tell me the details of dta cache? and what shall I do?  Best Regards!  FeiWu

[Altera_Forum]

I think it is a bug of Nios2 kernel. (Scott noted it in 2004.) 

Please update, __ioremap() in file arch/nios2nommu/mm/ioremap.c  /*  * Map some physical address range into the kernel address space.  */  void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag) {  return (void *)(physaddr | 0x80000000); // uncached }

[Altera_Forum]

--- Quote Start ---  originally posted by hippo@Oct 17 2006, 12:58 AM i think it is a bug of nios2 kernel. (scott noted it in 2004.) please update, __ioremap() in file  arch/nios2nommu/mm/ioremap.c  /*  * map some physical address range into the kernel address space.  */  void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag) {   return (void *)(physaddr | 0x80000000);  // uncached } <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18730)  --- quote end ---    --- Quote End ---    Maybe it will help. Below is a part of the Microtronix "readme.txt" file which states a data cache issue with uCLinux :  "...Notes and Known problems/limitations  1) Data cache line size must be 4 bytes. The other sizes (16 and 32) cannot  be used in a uClinux design. Using larger data cache line sizes result  in inconsistent values being read from memory.   The most obvious symptom is the paging filesystem not running properly.  The problem occurs at various times, sometimes early enough to prevent  kernel startup messages from appearing.   At this time the origins of the problem are still being investigated. "  BR

[Altera_Forum]

Tank you for you replies. 

I have readed the ioremap.c the __ioremap&#39;s code as follow: __ioremap() in file arch/nios2nommu/mm/ioremap.c  /* * Map some physical address range into the kernel address space. */  void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag) { return (void *)(physaddr);  } Hippo can you tell me why you change the code to "return (void *)(physaddr|0x80000000); "? I will regard your comment ,thank you

[Altera_Forum]

--- Quote Start ---  originally posted by smalllight@Oct 19 2006, 02:00 PM tank you for you replies. i have readed  the ioremap.c the __ioremap&#39;s code as follow: __ioremap() in file arch/nios2nommu/mm/ioremap.c  /* * map some physical address range into the kernel address space. */  void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag) { return (void *)(physaddr);  } hippo can you tell me why you change the code to "return (void *)(physaddr|0x80000000); "? i will regard your comment ,thank you <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18786)  --- quote end ---    --- Quote End ---   Smcnutt had noted ioremap() in this thread, http://forum.niosforum.com/forum/index.php...=735&hl=ioremap (http://forum.niosforum.com/forum/index.php?showtopic=735&hl=ioremap)  Next, look at the cfi flash map driver, linux-2.6.x/drivers/mtd/maps/altera.c nt __init init_alteramap(void) {  static const char *rom_probe_types[] = {"cfi_probe", "jedec_probe", 0 };  const char **type;   ndk_amd_map.virt = (unsigned long *)ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);  Look at the ioremap() and ioremap_nocache() in linux-2.6.x/include/asm-nios2nommu/io.h they all want the return be uncached address.  Though the mtd map use the uncached functions (from io.h) to access memory, linux-2.6.x/include/linux/mtd/map.h  Actually, the original code did not do anything about uncache. I could agree with that, if all the access are consistent. ie, always use the uncached functions (from io.h) to access memory, and never mix access with the cached virt address .

[Altera_Forum]

Dear Hippo, 

In my program, I didn&#39;t call the ioremap function directly, and I write the flash driver by myself. so I can&#39;t understand you clearly!  I&#39;m not familar with the cache! coud you please tell me more details about how the cache work?  Best Regards!  Fei WU

[Altera_Forum]

--- Quote Start ---  originally posted by feiwu@Oct 20 2006, 11:53 AM dear hippo,       in my program, i didn&#39;t call the ioremap function directly, and i write the flash driver by myself. so i can&#39;t understand you clearly!       i&#39;m not familar with the cache! coud you please tell me more details about how the cache work?       best regards!       fei wu <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18803)  --- quote end ---    --- Quote End ---   You have to set bit 31 of the flash address, in order to bypass data cache. That is, na_flash_kernel | 0x80000000 .  Actually, there is no need to write the flash driver. You should be able to use cfi mtd driver.

[Altera_Forum]

Dear Hippo, 

I had set the MSB (bit 31) of flash address to 1, but the netflash command still can&#39;t work correctly!  could you please give me more help?  Best Regards!  FeiWu

[Altera_Forum]

1. Is your board a custom board, or a dev board ? 

2. how do you call netflash ? which device? 3. do you use cfi core ? what is your flash chip? 4. you must always use uncached address to access flash, never mix with cached.

[Altera_Forum]

we are very grateful to you for your help. There are some bug in my flash driver.  

All the problem about netflash is ok now.