An Avalon DMA bug appears to exist in which the dma is only given 4 arbitration bus shares regardless of the share setting due to its fifo overflowing and terminating ownership of the bus.
This occurred with a non-burst dma configured on a bus with a non-pipelined clock, transferring from a ram with a 0-read/setup/write/hold and 3-pipelineread-latency to a register-device with 0 wait states.
The solution was to add
fifo_depth = "8";
to the altera_avalon_dma class.ptf
There are other major streaming DMA signal and documentation problems also which took several months of debugging.
Altera: It's annoying to debug half-incorrectly-documented stuff as important as streaming DMA that should be stable while corporate policy is to spend time creating new stuff. Reminds me of a company in Washington. Can I have a Quartus subscription for the 2 sleepless months of my life lost? I've noticed other posters say "finally gave up after several months".
I'll post the streaming DMA signal bugs when I get a little sleep.
