Dealing with multiprocessor cache coherency

[Altera_Forum]

Hi, 

 I am currently working on a system consisting of four Nios II/f processors. All these processors are configured with instruction and data cache. From what I understand the coherency of data cache in multiprocessor systems need to be managed by the designer. I have been searching on Altera website and on the net without much luck as to how to do this.  Can someone give me some ideas as to how this could be done?  Regards, Toby

[Altera_Forum]

Hi! 

 data coherency in multicore Nios II systems is not an easy task, because Nios II lacks cache coherency HW...  what you can do is to disable the cache, which often requires modifications to the source code...  What we have developed to solve this problem is to hidden the complexity of cache disabling to the user, giving the ease of use f single core architectures while working on a multicore system. If you are interested, you can get some information in the ERIKA Enterprise Manual, Section 3.8, page 33, available for download at the evidence literature page (http://www.evidence.eu.com/content/view/71/104/).  bye  Paolo

[Altera_Forum]

Hi Paolo, 

 Thank you for you advice. I have decided to without a d-cache for the mean time, will look into your suggestion in the future.  Regards, Colin