I am currently trying to design a small Nios II system on UP3 board which only consists of the Nios II/e core, jtag uart, timer and on-chip memory. The cyclone FPGA I use on UP3 board contains 92,000 memory bits that means there are about 11kb memory is avaiable.
However, every time when I compile the system, the maximum on-chip memory I can use is 4kb. The actual memory bit usage is only 46%. Whenever the size beyond 4kb, the compiler generates the error saying : Can't place 76 RAM cells or portions of RAM cells in design. Therefore most of the memory bits are unachievable and would be a wastage.
Anyone knows how to sort out this problem and is it possible to utilize the memory bits as much as possible?
