Innovation multi-channel DDCs IP core

[Altera_Forum]

innovation:  

32-Channel DDCs/64-Channel DDCs  The core is based on a novel channelisation architecture, which provides the flexibility traditionally associated with DDC cores and ASIC devices, but with significantly greater silicon efficiency,It Can be integrated into a single three million equivalent logic gates for Xilinx or Altera FPGA, in xilinx VirtexV6 devices or altera StratixIV devices can be integrated 1024-channel independent DDCs.    Specifications:  • Two 16-bit ADC inputs(for more inputs can custom), Fs > 220MS/s  • 64 independently configurable channels  • Independent tuning, gain, sample rate and output filter selection controls  • Output sample rates from Fs/128 to Fs/8192 or more  • Maximum alias-free output bandwidth of Fs/320 (= 625kHz for Fs = 200MS/s)  • 8 programmable output shaping filters  • Example filter performance: 0.1dB peak to peak ripple, alias-free bandwidth 80% of output sample rate and 90dB image rejection  • Centre frequency tuning accuracy to within 0.003Hz（Fs/2^36）  • Resampling provides any output rate to within 0.003Hz（Fs/2^36）  • >90dB spurious free end to end performance  • Resampled output maintains >90dB spurious free performance  • 0 to 90dB gain boost MGC & AGC    We can provide the logic netlist and HDL source code, technology does not transfer, thank co-operation.We can be different according to the customer's specific requirements such as bandwidth custom channel number (4/8/16/32/64 channels)      contact email: pornanier(at)163 point com