Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

Memory bits

Altera_Forum
Honored Contributor II
961 Views

Hi, 

 

I am using a cyclone 1 FPGA chip having about 290,000 memory bits. After I finished my design and while compilation with quartus, I get get an error printing the following message :"Error: Selected device has 64 RAM location(s) of type M4K RAM. However, the current design needs more than 64 to successfully fit." 

 

That's inspite the face that I have only used 180,000 memory bits which means I still got enough bits to use. What does that mean ? 

 

Thanks in advance
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
257 Views

Hi, 

First: Have enabled SignalTap? It needs memory bits in order to save the states. 

(It is a typical signal tap error) 

 

Second: I am not sure if you can combine memory blocks from several columns into one large chunk. 

 

I have never used cyc_I, so I am just guessing. 

 

g
0 Kudos
Altera_Forum
Honored Contributor II
257 Views

You can't count bits and determine how much more is available unless you are using all 9 bits of each byte. A 64x1 memory will consume all 4096+512 bits of an M4K just as a 512x9 will, but you only use 64 bits vs 4608, losing 4544 bits. If you are that tight on resource usage you will need to plan your design a bit more carefully. Remember that NIOS and JTAG UART with cache both use M4K as well as your added logic.

0 Kudos
Reply