Slow kernel boot-up (and slow SDRAM read transfer)

[Altera_Forum]

I am running a uClinux kernel from DDR2 SDRAM on a Cyclone II DSP Dev. Board.  

 I was having problems with slow boot-up previously when using Quartus 5.0.  I edited the em_epcs.pm and class.ptf file for EPCS by changing all instance of "extradelay = 1" to "extradelay = 0". This worked and lowered my boot time from about 2 min to under 10 seconds.   I just recently upgraded to Quartus 6.1. The em_epcs.pm and class.ptf files already had the "extradelay = 0" fix in them when installed. But now I'm back to a 90 second boot up time.   This slow boot time may or may not be related to a problem I have encountered when trying to perform pipelined reads from SDRAM with a custom-made master port in my Nios core. The time between reads is 8 26.25MHz clock cycles (at most I believe there should be 1 clock cycle between reads).   With Quartus 6.1 you can choose to pipeline any of the clocks in the Nios core. I pipelined the ddr2_clk that the SDRAM component runs off of but this didn't seem to make a difference to either problem.    Has anyone had similar problems - a slow boot up for your kernel or slow response from SDRAM read transfers??   Any help would be appreciated. Thanks

[Altera_Forum]

The current PIPELINE in SOPC is NO GOOD. 

It induced a long latency. Try remove all the PIPELINE.

[Altera_Forum]

My original design had no pipelining in SOPC. I added the pipeline when I saw this problem. So neither way is working for me.

[Altera_Forum]

UPDATE: 

I've tried running some of my older versions of this project (which used to boot quickly with Quartus 5.0) and they are booting very slowly as well. So it seems that this is a Quartus 6.1 problem...   Has anyone else run into this problem after upgrading Quartus?

[Altera_Forum]

I am still having problems with the kernel taking over 90 seconds to boot...but it's not essential that it be any faster so I'm not worrying about it for now.  

 HOWEVER, I am also still having problems reading data out of SDRAM fast enough. I need to read 1 64-bit word every clock cycle (26.25MHz). If I wait for the read_data_valid signal, I get 1 word every 8 clock cycles.  I created an avalon master port to perform pipelined master read transfers to retrieve the data from the DDR2 SDRAM on the Cyclone II DSP Board. I believe the problem lies somewhere in my state machine to control the master read transfer. I have read all the documentation i can find on how to do master read transfers but can't find my problem.  Does anyone have some example code they'd be willing to share?? Thanks.