Instantiate Max 10 ADC in VHDL

[Altera_Forum]

I'm sure this has been covered, but I can't seem to get Quartus to make the connection. I have a design that is 99% straight VHDL, but I need to monitor a couple of power supplies, so I routed scaled versions to the Max 10 ADC. I built a Qsys component for a simple ADC-only core and tried to instantiate it in my VHDL design, but I keep getting an error that an entity was used without being declared. 

 Now, I get that everything Quartus is generating is in Verilog, so I verified the case was correct, but still no dice. I know Quartus is aware of the ADC core because I see the messages about its generation during the build.  I named the core "lsm_emulator_adc", and it has a corresponding "lsm_emulator_adc.qsys" file which I brought into Quartus. I then mapped it in my HDL using a variety of methods, but at the moment:   U_ADC : entity lsm_emulator_adc.lsm_emulator_adc_modular_adc_0  port map (  adc_pll_clock_clk => ADC_Clock, -- adc_pll_clock.clk  adc_pll_locked_export => ADC_Locked, -- adc_pll_locked.export  clock_clk => SIM_Clock, -- clock.clk  command_valid => Command_Valid, -- command.valid  command_channel => Command_Channel, -- .channel  command_startofpacket => Command_SoP, -- .startofpacket  command_endofpacket => Command_EoP, -- .endofpacket  command_ready => Command_Ready, -- .ready  reset_sink_reset_n => Reset_n, -- reset_sink.reset_n  response_valid => Response_Valid, -- response.valid  response_channel => Response_Channel, -- .channel  response_data => Response_Data, -- .data  response_startofpacket => Response_SoP, -- .startofpacket  response_endofpacket => Response_EoP -- .endofpacket  );  I even tried declaring the component to see if that would resolve it, but so far no.  Can anyone help me figure out what I am doing wrong, or show me how to connect to the Max 10 ADC from a VHDL project?  Thanks!

[Altera_Forum]

In the parameter editor (Qsys) from the Generate menu, did you look at the instantiation template? That should help you out.  

 Can you post the component declaration and the exact error messages you're getting including messages just before the error?

[Altera_Forum]

Ok, well you were right. I missed something subtle in the instantiation file because I was used to doing it the regular way. 

 Using component instead of entity fixed it:   U_ADC : component lsm_emulator_adc  port map (  adc_pll_clock_clk => ADC_Clock, -- adc_pll_clock.clk  adc_pll_locked_export => ADC_Locked, -- adc_pll_locked.export  clock_clk => SIM_Clock, -- clock.clk  command_valid => Command_Valid, -- command.valid  command_channel => Command_Channel, -- .channel  command_startofpacket => Command_SoP, -- .startofpacket  command_endofpacket => Command_EoP, -- .endofpacket  command_ready => Command_Ready, -- .ready  reset_sink_reset_n => Reset_n, -- reset_sink.reset_n  response_valid => Response_Valid, -- response.valid  response_channel => Response_Channel, -- .channel  response_data => Response_Data, -- .data  response_startofpacket => Response_SoP, -- .startofpacket  response_endofpacket => Response_EoP -- .endofpacket  );  I'm not sure if including the library made a difference or not. It's still in the HDL, but it may not be necessary. Thanks for the hint!