Timing Contraint on latch

[Altera_Forum]

Anyone knows how to constraint the latch related circuitry? I attached a pdf that show the diagram. The clock is running at 10MHz and the timing requirements from input to output is 80nSec.

[Altera_Forum]

What is the purpose of this latch? Generally, using latches is not good design practice.  

     --- Quote Start ---  Anyone knows how to constraint the latch related circuitry? I attached a pdf that show the diagram. The clock is running at 10MHz and the timing requirements from input to output is 80nSec.  --- Quote End ---  

[Altera_Forum]

I know using latch is not good design and do not want to use. Unfortunately, I must use it for my application. I need to find out how I can constraint these latch. I was thinking of using set_max_delay, but I'm not sure whether this would do it since set_max_delay is used for combinatorial logic path.

[Altera_Forum]

--- Quote Start ---  I know using latch is not good design and do not want to use. Unfortunately, I must use it for my application. I need to find out how I can constraint these latch. I was thinking of using set_max_delay, but I'm not sure whether this would do it since set_max_delay is used for combinatorial logic path.  --- Quote End ---   Kattice, Yes, Latch IS a small combinational loop by itself.   just interesting, why you cannot use the flip-flop with Synchronous Clear, because, anyway, you latch by implication depends on the Clock - it clears after 5 clock cycles.  And for me it is looks strange to provide constraints for one specific module; what if you design contains 1000 logic gates, you cannot constraint each.