How to constraint clocks from the ASI IP Core?

Altera_Forum · ‎09-24-2009

I am using the ASI Recieve IP Core.

As the datasheet(ug_asi.pdf) suggests, I need to constraint three clocks: rx_serial_clk, rx_serial_clk90 and rx_clk135.(Actually rx_serial_clk and rx_serial_clk90 are from a pll and I think rx_clk_135 is also from there.)

In the Appendix, Page A-2, they give an example on how to constraint a clock, say like rx_serial_clk:

create_clocks -name {rx_serial_clk} -period 7.407 -waveform { 0.000 3.703 } [get_ports {rx_serial_clk}]

What if I take the clock 'rx_serial_clk' as an internal signal? You cannot get it throught a 'Port', right?

Then which command should I use instead of 'get_ports'?

Altera_Forum · ‎10-05-2009

You can try "get_registers" or "get_pins"?

Altera_Forum · ‎11-13-2009

I'm using the ASI core in a Cyclone III, try something like this:

derive_pll_clocks -create_base_clocks

set rx_clk135 "ASI_RX_PLL_1|altpll_component|auto_generated|pll1|clk[0]"

set rx_serial_clk "ASI_RX_PLL_1|altpll_component|auto_generated|pll1|clk[1]"

set rx_serial_clk_90 "ASI_RX_PLL_1|altpll_component|auto_generated|pll1|clk[2]"

set_max_delay -from $rx_serial_clk -to $rx_clk135 4.430;

set_min_delay -from $rx_serial_clk -to $rx_clk135 0.000;

# added this to make sure the sample_a/b/c/d registers were not located in the wrong place. :-)

set_max_delay -from ASI_RX_Pi

[*] -to * 4.50;

Don't forget to add the location constraints for the sample_a, sample_b, sample_c, and sample_d registers too.