Why use DSP builder over HDL

[Altera_Forum]

So, its come to a point where management are insisting all implementation is done in Simulink/DSP builder, rather than hand coded HDL. 

 Ive been using DSP builder in simulink a week now, and all I feel is like its come full circle back to schematic entry that many people abandoned for HDL input years ago. We lose the ability for auto-documention of changes via version control, but it appears we gain commonality inside a single environment accross all departments. But even that doesnt fully ring true, as simulink allows co-simulation of HDL via modelsim.  So guys (and any girls?) why advantages does simulink/DSP builder offer me over well written, well structered HDL?

[Altera_Forum]

So, like anything, there are a lot of possible answers to this. In case you weren't aware, DSP Builder has two tools: DSP Builder and DSP Builder Advanced Blockset which changes my opinion some. 

 Generally, the benefit of Simulink I believe is the simulation environment. Its much faster that modelsim and is much easier to generate vectors, apply them and collect the result. Sweeping parameters for things like fixed point analysis and filter lengths, sample rates, is also easier. This works well for algorithms which are somewhat feedforward with relatively light control. Your not going to replace a DSP with DSP builder, but a upconverter is rather straightforward  DSP Builder (Standard) is a WYSIWYG type flow which you could argue is schematic like, other than the fact it allows you to have some high level models and manage your types. DSP Builder Advanced Blockset is an entirely different beast. This tool does all sort of things you cant do in HDL. Namely, it allows you to describe an algorithm without any FPGA type constructs:  - no pipelining: the data flow is described with no pipelining, just algorithmic latency, the selected device and desired clock rate allows the tool to pipeline and balance the delays to meet your fmax target. - implementation tradeoffs: for things like memories and multipliers, you can specify a threshold number of logic elements above which the memory or multiplier is implemented in hard blocks, but otherwise can be done in the logic fabric. - processor bus generation: You can drop down 'source' and 'sink' blocks that will get rolled up into an Avalon MM Slave without any hand coding. - vector / array support: you can use vectors and do vector math. limited number of blocks now, but you can build your own pretty easy as the tool can work with the math -complex support: self explanatory. This means you can filter 16 channels of I and Q data against a real filter with effectively 1 block. -folding/ automated TDMing: this is the coolest one. You do your design completely parallel and specify a sample rate. The tool can look at the FPGA clock rate relative to the specified sample rate and timeshare the memories and multipliers to reduce the size of the design.  (the last 3 items are in the 9.1 release next month I think)   I think the key thing with the advanced blockset is it allows 'portable' IP. Not to another tool obviously, but if you find a small requirements change, change devices or move to a new FPGA family with different resources retargeting takes 5 minutes. Its also nice when you find out at the end of the design you've under or overestimated your potential fmax, so you can 'refold' your design on the fly to reduce the resources if it turns out you could run faster, or lower your fmax and refold without throwing out all your old code as with RTL.  x

[Altera_Forum]

--- Quote Start ---   Generally, the benefit of Simulink I believe is the simulation environment. Its much faster that modelsim and is much easier to generate vectors, apply them and collect the result. Sweeping parameters for things like fixed point analysis and filter lengths, sample rates, is also easier. This works well for algorithms which are somewhat feedforward with relatively light control. Your not going to replace a DSP with DSP builder, but a upconverter is rather straightforward   --- Quote Start ---    I do see this as a great advantage of Simulink in general. The ability to model an entire system and create behavioural architectural models is great, especially when it comes to black box testing. What I dont like simulink/dsp builder for is actual implementation when it is slightly outside of the scope of the existing blocks. Building a design from primitives goes back to the old days of Quartus schematic entry (or at least it feels like it). Also, with the new IEEE fixed point library I can see at a glance what range a signal/variable exists in, rather than having to go through the paramenters for each block.

[Altera_Forum]

I agree with you overall. I do think when you start talking about something like what the Advanced blockset is doing where you don't do any timesharing manually, your not doing any timing or pipelining, and generally do a purely functional design without any FPGA 'stuff' its not really schematics. 

 But none-the-less, there are some applications where it still won't make sense.