I am trying to return a simple 1 DW read transaction to the host in a simulation with the Altera PCIe core x8 gen2 endpoint generated with quartus 9.0sp2. I receive the read request, handle it, and submit a completion to the tx_st interface. However, shortly thereafter the tx_fifo_empty0 output goes U, as does tx_fifo_rdptr0, and the response never gets to the root BFM. All inputs to the endpoint are driven. My completion looks ok when compared with the chaining dma example design simulation. What could cause this behavior?
First picture is RD32 TRN, second is my completion.
Thanks,
