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Attached are some plots comparing FIR Compiler v8.0 and FIR Compiler v3.3.1 interpolate by 2 FIRs.
Has anyone else seen this problem? Has anyone successfully generated interpolation FIRs with FIR Compiler v9.0? From the latest MegaCore IP release notes and errata: Incorrect Results for Multi-Bit Serial or Interpolation with Signed Binary Fractional Incorrect results when Structure is set to Distributed Arithmetic: Multi-Bit Serial Filter or the Rate Specification is set to Interpolation, and Signed Binary Fractional is specified for the data type. Simulation Result Incorrect Using MCV Interpolation Filters Some multicycle variable interpolation filters with high interpolation factors may generate incorrect output. Incorrect Output for Signed Binary Fractional Multi-Bit Serial or Interpolation Filter The FIR Compiler output data is incorrect if you choose Signed Binary Fractional data type with Multi-Bit Serial Filter structure or Interpolation rate specification. No mention of problems with signed binary and low interpolation factors, so I suspect the problem will be present in FIR Compiler v9.0 also.Link Copied
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Did you look at this document ?
http://www.altera.com/literature/rn/rn_ip.pdf Chapter 9 page 61 There is a bug listed about incorret mcv simulation still present in Quartus V9 Did you contact MySupport ?- Mark as New
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--- Quote Start --- Did you look at this document ? http://www.altera.com/literature/rn/rn_ip.pdf Chapter 9 page 61 There is a bug listed about incorret mcv simulation still present in Quartus V9 Did you contact MySupport ? --- Quote End --- Yes rn_ip.pdf was the document I was referring to in my previous post, and the MCV bug you mention is only for large interpolation factors. The bug I am experiencing occurs for both MCV and DA architectures, and I have an interpolation factor of 2 set. I have contacted MySupport about this.
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