Pausing target processor not responding in stratix 2

Altera_Forum · ‎10-07-2009

Hi all,

Im a new user in FPGA board. Currently i have a problem regarding my project. I able to generate and download my .sof file into my fpga board without any error. Then i also manage to build a nios-ide project template, "small hello world" without any error but the problem occurs when i run the program in hardware the following message appear on th nios-ide console window.

" Using cable "USB-Blaster [USB 6-1.1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused "

These are the following hardware, software and nios 2 system that i had included in my project:

Hardware and Software:

1) OS: linux-ubuntu 9.04

2) Quartus II version 9.0 SJ full version

3) Nios II Integrated Development Environment Version: 9.0

4) Stratix II, EP2S60F672C3

Nios 2 system's peripheral

1) cpu (**clock setting= ddr_sdram_sysclk=100Mhz)

2) DDR SDRAM ,(Micron Mt46v16m16tg-6t), 16 bits wide, discrete device, CAS 3.0, 1 chip select. (**clock setting= clk=50Mhz)

3) high_res_timer - (timeout period =10us..counter size=64 bits.. full featured) (**clock setting= ddr_sdram_sysclk=100Mhz)

4) sysid (**clock setting= ddr_sdram_sysclk=100Mhz)

5) jtag_uart (read and write FIFO .buffer depth=64 bytes)

(**clock setting= ddr_sdram_sysclk=100Mhz)

I been trying to solve this problem for 3 weeks. I tried using Quartus 8.0, another stratix 2 board and different PC but i get the same error message. I will be very thankfull if any one of you guy manage to solve my problem.. Thank you.... :)

Altera_Forum · ‎10-07-2009

Hi,

Very first check the following two things.

1) CPU clock is working or not

2) Reset pin not active all the time.

Altera_Forum · ‎10-07-2009

The CPU clock is working and the reset pin is set to pin_aa15. The design is working when i use "on chip memory" but i have that error when i add DDR SDRAM.

Altera_Forum · ‎10-07-2009

have you tried with design example provided by altera for Nios II development kit for 2S60 board ?

You can get ready made system from <Nios installation dir>\examples\verilog

Try simple c program with DDR as program memory using this system.

Altera_Forum · ‎10-07-2009

Yes Hardik, I am running the design example "small Hello World" provided by altera for Nios II development kit for 2S60 board.... :) Hardik i manage to figure out the problem.

Altera_Forum · ‎10-07-2009

Here how it goes, previously i mentioned that i can run the program using "on chip memory" and the problem occurs when i add DDR SDRAM. So it seems like i have problem with my DDR SDRAM. I figure out that my problem is caused by my top level module which i wrongly assign one of the signal, "global_reset_n_to_the_ddr_sdram". i had include my top level module for your view.....but i need some explaination based on this problem ?? All the best for all beginers like me... :)

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module system(

// 1) global signals:

clk, reset_n,

// the_ddr_sdram_0

ddr_a, ddr_ba, ddr_cas_n, ddr_cke, clk_to_sdram_n, clk_to_sdram, ddr_cs_n, ddr_dm, ddr_dq, ddr_dqs, ddr_ras_n, ddr_we_n );

// 1) global signals:

input clk; input reset_n;

// DDR SDRAM

// i/o signal

output [12: 0] ddr_a; output [ 1: 0] ddr_ba; output [ 1: 0] ddr_cas_n; output [ 1: 0] ddr_cke; inout [ 1: 0] clk_to_sdram_n; inout [ 1: 0] clk_to_sdram; output [ 1: 0] ddr_cs_n; output [ 1: 0] ddr_dm; inout [15: 0] ddr_dq; inout [ 1: 0 ] ddr_dqs; output [ 1: 0 ] ddr_ras_n; output [ 1: 0 ] ddr_we_n;

//wires wire

ddr_sdram_aux_full_rate_clk_out; wire ddr_sdram_aux_half_rate_clk_out; wire ddr_sdram_phy_clk_out; wire dll_reference_clk_from_the_ddr_sdram; wire [ 5: 0] dqs_delay_ctrl_export_from_the_ddr_sdram; wire local_init_done_from_the_ddr_sdram; wire local_refresh_ack_from_the_ddr_sdram; wire local_wdata_req_from_the_ddr_sdram; wire reset_phy_clk_n_from_the_ddr_sdram; wire global_reset_n_to_the_ddr_sdram;

system_file the_system_file

( //global signals:

.clk (clk), .reset_n (reset_n),

//DDR SDRAM

//wires

.ddr_sdram_aux_full_rate_clk_out (ddr_sdram_aux_full_rate_clk_out), .ddr_sdram_aux_half_rate_clk_out (ddr_sdram_aux_half_rate_clk_out), .ddr_sdram_phy_clk_out (ddr_sdram_phy_clk_out), .dll_reference_clk_from_the_ddr_sdram (dll_reference_clk_from_the_ddr_sdram), .dqs_delay_ctrl_export_from_the_ddr_sdram (dqs_delay_ctrl_export_from_the_ddr_sdram),

//HERE IS THE CHANGES THAT I HAD MADE

// .global_reset_n_to_the_ddr_sdram (global_reset_n_to_the_ddr_sdram),

.global_reset_n_to_the_ddr_sdram (reset_n),

.local_init_done_from_the_ddr_sdram (local_init_done_from_the_ddr_sdram), .local_refresh_ack_from_the_ddr_sdram (local_refresh_ack_from_the_ddr_sdram), .local_wdata_req_from_the_ddr_sdram (local_wdata_req_from_the_ddr_sdram), .reset_phy_clk_n_from_the_ddr_sdram (reset_phy_clk_n_from_the_ddr_sdram),

//io signals

.mem_addr_from_the_ddr_sdram (ddr_a), .mem_ba_from_the_ddr_sdram (ddr_ba), .mem_cas_n_from_the_ddr_sdram (ddr_cas_n), .mem_cke_from_the_ddr_sdram (ddr_cke), .mem_clk_n_to_and_from_the_ddr_sdram (clk_to_sdram_n), .mem_clk_to_and_from_the_ddr_sdram (clk_to_sdram), .mem_cs_n_from_the_ddr_sdram (ddr_cs_n), .mem_dm_from_the_ddr_sdram (ddr_dm), .mem_dq_to_and_from_the_ddr_sdram (ddr_dq), .mem_dqs_to_and_from_the_ddr_sdram (ddr_dqs), .mem_ras_n_from_the_ddr_sdram (ddr_ras_n), .mem_we_n_from_the_ddr_sdram (ddr_we_n) );

endmodule

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