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Hi,
I'm using a UART 16550 core from opencores in the SOPC builder, works very fine. It has build-in rx/tx FIFO, 16 Byte each. Quartus II uses a whole M9K-Block, which means a lot of wasted RAM. My Cyclone 3 is half full in LEs, but I could use more RAM. Long story short, I did not found a way to tell Quartus to use Logic Elements for this memory. Is this not possible here? I've tried the Assignment "Auto RAM to Logic Cell Conversion" but this didn't work. The RAM is inferred as follows:module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input a;
input dpra;
input di;
//output spo;
output dpo;
reg ram ;
wire dpo;
wire di;
wire a;
wire dpra;
always @(posedge clk) begin
if (we)
ram <= di;
end
// assign spo = ram;
assign dpo = ram;
endmodule
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If you use the megawizard to instantiate a ram, rather than inferring it, there is a tick box which allows to choose LEs or M9Ks.
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Turn off "Auto RAM replacement" and turn on "Auto RAM to Logic Cell Conversion" too.
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Ben:
Thanks, I just found it out by myself just as you were posting. I've inferred a altdpram with the Megawizard now and it works great. Saves a lot of memory.- Mark as New
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the Verilog ramstyle synthesis attribute is also worth looking at.
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