PLL operating range

[Altera_Forum]

i am in the need to deskew or multiply the frequency of an input clock whose frequency can vary widely. the application is video where the clock can be coming in LVDS or LVTTL at clock speeds varying from as much as 13MHz->165 MHz. clearly Altera PLLs don't support such a wide range so i was wondering if there is any workaround that would allow dynamically reconfiguring PLLs based on the input clock frequency without the need for an external fixed frequency reference clock. 

for example in one application i have to receive a Panellink input 28:4 multiplexed LVDS data (each pair contains 7 bits) and for that i need to be able to multiply the input clock by 3.5 however due to the extreme variability of the input clock the PLL of course ma not lock poperly

[Altera_Forum]

What device do you mean? Stratix PLLs input frequency range is 3 - 462 MHz, and PLL reconfiguration is supported.

[Altera_Forum]

question is pretty generic, not related to a specific device. i know PLL frequency range is wide however with a given setup it's pretty narrow and the worse thing is that the PLL may eventually lock onto a multiple frequency of the input. for example say you want to implement an input that accepts input frequencies say from 25 to 100 MHz and PLL is used to multiply this by a given factor (for panel link it's 7). in this case it seems to me the only way is to have a reference crystal to measure input frequency and reprogram PLL parameters accordingly which is a bit complex to do and adds latency in the lock acquisition process.  

thanks!  Dario

[Altera_Forum]

--- Quote Start ---  which is a bit complex to do and adds latency in the lock acquisition process.  --- Quote End ---  Complex, yes. Lock delay can be expected with any PLL, also of existing DVI hardware. Shouldn't be a problem, I think.

[Altera_Forum]

well i guess the answer is there's no other way to do it. it's a pity as assuming 20MHz safe range from nominal frequency it would mean that we need to have at least 8 different settings to span up to 165 MHz. lock time is normal however to this we need to add the time required to reconfigure the PLL and add a reference clock to our system (although i agree that in most system you do have a reference clock anyway).

[Altera_Forum]

This document http://www.altera.com/literature/cp/cp-01051-pll-adaptation.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=method and Apparatus of 

 might have some hints