Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
1175 Discussions

up_ip_core help me!

Altera_Forum
Honored Contributor II
‎10-08-2009 04:41 PM
940 Views

Hi! 

 

I have a DE2-70 board with Quartus 9.0 + nios2 IDE 9.0. I'd like to design a nios2 cored system with up_ip_core 9.0. works on 100MHz and that must be control all board's component resources (vga, lcd, ethernet etc.). So all components on board can be controlled with a suitable software running on nios2 unless changing the FPGA hardware structure. What must the clock sources be for all components or how can I set the suitable clock sources for each component and pipeline bridge ? Do you have any example of this or source matterial.?  

 

thanks for your helps.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-10-2009 07:36 PM
258 Views

As far as I know there is no single precooked design that illustrates all of the features that you mentioned. The best starting point for the DE2-70 is the accompanying cd-rom (http://www.terasic.com/downloads/cd-rom/de2_70/). It has a number of sample projects in source code that illustrate the use of most of the peripherals of the DE2-70 system.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.