SOPC ERROR: Cannot have an associated clock

Altera_Forum · ‎10-09-2009

Hi,

I'm trying to generate a SOPC component from a VHDL file. I want to make an I2C component. The VHDL basis ist the I2C Master/Slave from opencores. I modified it in that way, that I only need an I2C master that is writing data to the bus.

Here is my port definition:


ENTITY i2c_core_v02_master_write IS
  generic
    (
     CLK_FREQ : natural := 25000000
    ); 
  PORT
    ( 
     --INPUTS
     csi_clock_clk	 : IN	std_logic; -- The signals obey the naming conventions specified in the Quartus II Handbook Volume 4: SOPC Builder
     csi_rst_reset	 : IN	std_logic;
     avs_start_begintransfer : IN	std_logic;
     avs_stop_begintransfer : IN	std_logic;
     avs_write_write : IN	std_logic;
     avs_data_writedata : IN	std_logic_vector (7 DOWNTO 0);       
     --OUTPUTS
     coe_sda_export : INOUT	std_logic;
     coe_scl_export : INOUT	std_logic;
     avs_ready_readyfordata : OUT	std_logic;
     avs_flags_readdata : OUT	std_logic_vector (7 downto 0); -- Field 0 contains the acknowledge information
     avs_acknowledge_dataavailable : OUT	std_logic
    );
END ENTITY i2c_core_v02_master_write;

As you can see, I tried using the naming conventions so that SOPC builder should be able to create the component with the correct interfaces and signal types. Unfortunatly, when I put this file into the New Component dialog of SOPC builder, I get the following Messages:

<html>Error: .rst: Cannot have an associated clock

<html>Warning: .start: Slave has no read or write interface

<html>Warning: .stop: Slave has no read or write interface

<html>Warning: .write: Slave has no read or write interface

<html>Warning: .write: Has write but no writedata signal

<html>Warning: .data: Has write interface but no write control

<html>Warning: .ready: Slave has no read or write interface

<html>Warning: .ready: Slave has readyfordata signal but cannot accept writes

<html>Warning: .acknowledge: Slave has no read or write interface

<html>Warning: .acknowledge: Slave has dataavailable signal but cannot read

I don't know, what I have done wrong. I don't know either what to do about the error nor the warnings. I don't find any information in the web or in this forum. It seems as if no one but me has ever got such output from SOPC builder.

I'm using the altera documentation but it does not tell anything about warnings and errors and what to do about them.

Please, somebody tell me what I'm doing wrong here.

Maik

Altera_Forum · ‎10-09-2009

The second part of the signal name should be the interface name, and should be the same for all the signals in one interface. In your case you could use those signal names:

     --INPUTS
     csi_sysclk_clk	 : IN	std_logic; -- The signals obey the naming conventions specified in the Quartus II Handbook Volume 4: SOPC Builder
     csi_sysclk_reset	 : IN	std_logic;
     avs_avalon_read : IN	std_logic;
     avs_avalon_write : IN	std_logic;
     avs_avalon_begintransfer : IN	std_logic;
     avs_avalon_writedata : IN	std_logic_vector (7 DOWNTO 0);       
     --OUTPUTS
     coe_i2c_sda : INOUT	std_logic;
     coe_i2c_scl : INOUT	std_logic;
     avs_avalon_readyfordata : OUT	std_logic;
     avs_avalon_readdata : OUT	std_logic_vector (7 downto 0); -- Field 0 contains the acknowledge information
     avs_avalon_dataavailable : OUT	std_logic

I'm not sure you need all the begintransfer, readyfordata and dataavailable, but it depends on how you do your IP.

Not everything is picked up by the component editor, you'll at least have to declare manually the export signals, and maybe associate the avalon interface with the correct clock.

Altera_Forum · ‎10-09-2009

Hi Daixiwen,

I'm a little bit confused. . . .

I will try to implement my port list as you suggested, but I have to think about it because I can't do it exactly like you suggested.

In the meantime, I wonder, why I have to name the second part of the interface name as you suggested. In the Quartus II Handbook Version 9.0 Volume 4: SOPC Builder on page 6-4 it is said that "For any value of <interface_name> the component editor automatically creates an interface by that name.

I thought that this is the part of the naming convention, where I can choose my own name for the port (or better pin), which I can bind to the actual function it has.

I also don't understand why you suggest something like this:

coe_i2c_sda

instead of the original

coe_sda_export

where the first part is the interface type (-> coe, conduit), the second part is the actual interface name that I chose (-> sda) and the last ist the signal type (-> export) which defines that this pin is connected to external logic . . . E.g., I totally miss this "export" in your suggestion.

Maik

Altera_Forum · ‎10-09-2009

I don't disagree with the SOPC builder manual. For your component, you must declare 3 interfaces:[list][*]a clock/reset input[*]an Avalon memory mapped slave[*]an export interface[/list]Each signal falls in one of those interfaces, and all the signals that are part of one interface must share the same interface name. That way they will all be regrouped by the component builder.

It is more difficult to follow the same convention with the export signals, as they would be all called "export". You could either declare a specific interface name for each individual signal (coe_sda_export, coe_scl_export) or put them all in one export interface and choose not to follow the convention. I usually choose the latter option.

Altera_Forum · ‎10-09-2009

Hi again,

thanks for pushing me into the right direction . . .

I just renamed my port map the way you suggested it and I don't have any errors and warnings anymore.

For my VHDL module, that means that I have to rewrite some parts because it was meant to work a little bit different than I have to use it, now. But this should be possible.

I wonder, how I can provide something like acknowledge to the Avalon system as there is no such signal type.

Is it an uncommon request to have an acknowledge signal available?

Well i try to figure out how all this is meant to work, therefore I appologize if I appear a little bit unexperienced.

Maik

Altera_Forum · ‎10-09-2009

Traditionally you have two ways oy handling timing on an avalon slave interface.

The first way is to use fixed timing. In that case you only use the read and write signals, with no acknowledge, and you specify in the component builder how many cycles are necessary for a read or a write operation.

The other one is to use the waitrequest signal. In that case, as soon as you have the read or write request, you assert waitrequest, and the master will wait. When the read or write operation is finished, de-assert waitrequest. I guess this is the closest to the acknowledge that you want to implement.

All this is well described in the avalon interface specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf).

Altera_Forum · ‎10-09-2009

Thanks again!

I guess, I have to get used to the concepts that are behind this avalon specification. I have to figure out how I can achieve what I need to do with these interfaces that are provided. If I need something else, I have to think about implementing it differently.

Up to now, i was just developing in pure VHDL and that gave me all the possibilities I needed because I was able to define the interfaces between components by myself. . . .

Maik