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Hi,
I found that it is not possible to synthesis VHDL wait statement in quartus 2. Is there any other alternative for this. What I am trying to do, is to generate some signals as shown in attached picture. Thanks in advance!Link Copied
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The wait statement was never put in to be synthesisable. It is there for modeling purposes only.
The easiest (and with FPGAs, probably the only way) is to use a clock and then you can syncronise all logic. This means you can garantee waiting times through counting clock cycles.
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