I have created a PCB using a Max II EPM240T100I5N for a state machine + logic. It works 100% except for the fact that the outputs are high for 100us in duration (1 clock cycle) at startup. The State machine startsup into a reset state where all outputs are explicitly forced to low at. Is there a Quartus setting that I haven't checked that suppresses the outputs at startup or is this something I will have to live with. Its not a trainsmash as the other systems which interface with the board have not yet initialised when the glitch occurs and therefore are incapable of responding or even detecting it, but I would like to sort out this issue nonetheless. The outputs are driving nchannel FETs with 10k pull downs at the gate. Any help would be appreciated Meng
It's very simple. According to the datasheet, MAX II I/O pins have pull-up resistors, that source up to 300 uA in unconfigured state. This also apply to the short intervall between power-up and entering user mode. Usually a 1-2k pull-down resistor is sufficient to override the weak pull-up. Another option is using active low outputs and external inverters.
Sounds like you misunderstood the problem. Initialization isn't an issue here. It's basically a question of hardware behaviour, not related to HDL programming.
I suspected it was the pins tri-stating at startup, but I assumed there was a way to override this behavior. Probably not going to bother changing the pull-downs (no issues with the glitch yet) Many thanks for the advice Meng
