cycloneIII I/O error in Quartus 9.1 while cycloneII succeed.

[Altera_Forum]

I use alt_inbuf with cycloneIII got this error: 

  --- Quote Start ---   Error: The location assignment on the I/O primitive instance "pad_in_pullup_cell_01" specifies an exact pin location. This is not supported for the Cyclone III family in the current version of the Quartus II software. File: /home/write-able/3/src/top.v Line: 20    --- Quote End ---  If I change to use a cycloneII, all OK. Does anyone know why ?  https://www.alteraforum.com/forum/attachment.php?attachmentid=1651   https://www.alteraforum.com/forum/attachment.php?attachmentid=1652     --- Quote Start ---    //------------------------------------------ //------------------------------------------ //------------------------------------------ //------------------------------------------  module pad_in (  SPAD,  in_inside ); input SPAD ; output in_inside ;  //------------------------------------------ wire SPAD ; wire in_inside ; //------------------------------------------  alt_inbuf pad_in_pullup_cell_01 (   .i ( SPAD ),  .o ( in_inside ) ); defparam pad_in_pullup_cell_01.io_standard = "3.3-V LVCMOS" ; defparam pad_in_pullup_cell_01.location = "PIN_149" ; defparam pad_in_pullup_cell_01.enable_bus_hold = "off" ; defparam pad_in_pullup_cell_01.weak_pull_up_resistor = "off" ; defparam pad_in_pullup_cell_01.termination = "NONE" ;    endmodule  //------------------------------------------ //------------------------------------------ //------------------------------------------ //------------------------------------------  module pad_out (  SPAD ,  out_inside ); output SPAD ; input out_inside ;  //------------------------------------------ wire SPAD ; wire out_inside ; //------------------------------------------  alt_outbuf pad_out_cell_01 (   .o ( SPAD ),  .i ( out_inside ) ); defparam pad_out_cell_01.io_standard = "3.3V LVCMOS"; //defparam pad_out_cell_01.location = "MAXIMUM CURRENT"; //defparam pad_out_cell_01.location = "PIN_87" ; defparam pad_out_cell_01.enable_bus_hold = "off"; defparam pad_out_cell_01.weak_pull_up_resistor = "NONE";  //defparam pad_out_cell_01.termination = "series 25 ohms";  defparam pad_out_cell_01.termination = "NONE"; defparam pad_out_cell_01.slew_rate = -1; defparam pad_out_cell_01.slow_slew_rate = "NONE";  endmodule  //------------------------------------------ //------------------------------------------ //------------------------------------------ //------------------------------------------  module top (  in ,  out ); output out ; input in ;  //------------------------------------------ wire out ; wire in ; //------------------------------------------ wire ww1 ; //------------------------------------------  pad_in pad_in01 ( .SPAD ( in ) , .in_inside ( ww1 ) ); pad_out pad_out01 ( .SPAD ( out ) , .out_inside ( ww1 ) );  endmodule  //------------------------------------------ //------------------------------------------ //------------------------------------------ //------------------------------------------     --- Quote End ---  

[Altera_Forum]

Are there Altera Quartus's people ? 

Do you think the quartus runs error , or the usage of the cycloneIII's I/O pins' location in my verilog HDL is error ?

[Altera_Forum]

Do you have a particular reason not to use the standard method to assign pin locations? It's convenient with the Pin Planner tool.

[Altera_Forum]

What's the "standard" method ? 

 I am a ASIC designer. I always works under CLI , or Altera called command console mode.  I never use GUI of Quartus before when I use cycloneII. And all works well.  But, now, I change to use cycloneIII, I failed, for the Quartus software ! Or , not the software ? Do you change the pin assign mode under CLI ?