Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12589 Discussions

Why nios ii program execution time, sometimes fast, sometimes slow?

Altera_Forum
Honored Contributor II
983 Views

We use the nios ii 7.2 multi-processor, using the chip is epc3c25-384c8, cpu clock signal for the 50mhz, using assembly language, when the implementation of the interrupt program, the program execution time is sometimes fast and sometimes slowly, the most time of 70us , the shortest time is 50us, cache for the 4k, we ask to improve procedures for real-time, how to solve this problem? Thanks:confused:

0 Kudos
8 Replies
Altera_Forum
Honored Contributor II
309 Views

so didn't say much about the implementation of your multi processor system, but could ist be that the variantion comes from any kind of arbitration logic that controls the access of the different cores and puts one into waiting for a resource while another one is using it ?

0 Kudos
Altera_Forum
Honored Contributor II
309 Views

In this system inside, a total of three processors, two of which cpu the program memory sram is external, and the bus is independent, and the other a cpu program memory using fpga internal sram.

0 Kudos
Altera_Forum
Honored Contributor II
309 Views

and what about data memories or any other ports or registered shared between these cores ? is there anything they share ?

0 Kudos
Altera_Forum
Honored Contributor II
309 Views

In this system, there are three cpu, we call xcpu ycpu and zcpu, xcpu and ycpu between the dual-port ram sharing, ycpu and zcpu are also among the shared dual-port ram.

0 Kudos
Altera_Forum
Honored Contributor II
309 Views

Now xcpu require real-time highly, 100us interrupt time, the program run time-critical, can not exceed a certain time

0 Kudos
Altera_Forum
Honored Contributor II
309 Views

does this cpu has some kind of caches ? 

maybe cache flush when entering interrupt
0 Kudos
Altera_Forum
Honored Contributor II
309 Views

Thank you,  

When xcpu into the disruption, we use the oscilloscope to see the external sram read signal line, there are signals, as if reading an external program, why read buffer will extend the program execution time? In addition, we found that interruption of proceedings, only a few programs , but the actual execution time of more than a theoretical program execution time, how to solve this problem? This is a nios own shortcomings, or do we design problem?
0 Kudos
Altera_Forum
Honored Contributor II
309 Views

THANKS 

 

I question the premise, why enter the interrupt program, the program execution time is sometimes fast, sometimes slow, the problem we have now is not resolved, there is no way in the circumstances, the clock frequency from the original 50mhz raised to 80mhz, also quarts -ii soft would version upgrade from the original 7.2 upgrade to 9.0, but in the case of 80mhz can not run, but the cache from the original 8k reduced to 4k, can run at 80mhz, but this way, reducing the cashe, program execution time and slower, and we feel this is a contradiction, we use the assembly language, can not be used c2h, please help us, thank you 

http://www.alteraforum.com/forum/showthread.php?t=19389
0 Kudos
Reply