ModelSim: No Output

[Altera_Forum]

Hi. I try to simulate a design. there is output in Quartus II(Timing Simulation). But not in modelsim. May i know the reason? i am just new to modelsim.. 

 FYI, my design just need the input of clock. So, i doesn't design the testbench. I just simulate the design without testbench. I just assign the clock with 1u period.  In this case, do i need to design the testbench?  Thanks

[Altera_Forum]

To run the simulation in Modelsim, you need to write a testbench.

[Altera_Forum]

You don't necessarily need a testbench. You can assign a clock waveform to an input signal using the clock command. 

 Select your signal in the wave window, or in the object pane of the main window, right click to get a context menu, and select the clock menu item.  A testbench will make your life easier though. For a trivial testbench like this, you can embed it in your top entity/module, if you want.

[Altera_Forum]

I did as what u told previously as i mentioned before "I just assigned the 1u period for the clock". The results turns out nothing. So, i just wonder why.

[Altera_Forum]

Sorry, I missed you did that already. 

 What you mean by it turns out nothing?  Make sure you run the simulation long enough. The default simulation time for ModelSim is usually smaller than 1 microsecond.

[Altera_Forum]

the result is zero for all my output.  

 The simulation i ran was 3s.

[Altera_Forum]

Please forgive me if some of the comments are too obvious, but I'd mention them just in case: 

 Do you see the clock waveform for the input clock signal? If you don't, then something is very wrong and focus on getting the clock waveform before anything else. Note that you must perform the "clock" command on every single simulation run, each time you restart simulation. Also make sure you are not "zooming" too much (yeah, too obvious, but it happened to me a couple of times).  Check if you don't have a global async reset that is resetting all the flip-flops.  Check for implicit power-up register values. FPGA registers power-up to zero by default. Quartus simulator (I believe) is aware about that, but ModelSim doesn't. Unlikely that this is the problem, because if so you would probably get X (unknown) as your outputs, and not zero.  Are you using/simulating a PLL? If so, then simulation time units must be 1ps.

[Altera_Forum]

It works d. It is due to the initialization of reg as u mentioned. By the way, if i change the source directory, how to refer it back from the modelsim. 

 Thanks a lot