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generate a .vqm file

Altera_Forum
Honored Contributor II
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hi, 

i am using a Cyclone II FPGA and i want to generate a vqm file by the Quartus II Compiler. When i compile my design , sometimes a ASCII text file is created, and sometimes a binary file. what should i do in order to create a ASCII text file,instead of a binary file?
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

hi, 

i am using a Cyclone II FPGA and i want to generate a vqm file by the Quartus II Compiler. When i compile my design , sometimes a ASCII text file is created, and sometimes a binary file. what should i do in order to create a ASCII text file,instead of a binary file? 

--- Quote End ---  

 

 

 

Hi suplina, 

 

choose : Assignments -> Settings -> Compilation Process Settings ->  

"Save a node-level netlist of the entire design into a persistent source file" 

 

Quartus will create a new directory "atom_netlist". You will find the vqm file in this 

directory. 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

Hi suplina, 

 

choose : Assignments -> Settings -> Compilation Process Settings ->  

"Save a node-level netlist of the entire design into a persistent source file" 

 

Quartus will create a new directory "atom_netlist". You will find the vqm file in this 

directory. 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

hi, 

Thank you for your answer, i have done what you told me and created two different vqm files for two different modules,however,it is strage that one of the vqm file is full of messy code ,and the other shows normal,why?
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

hi, 

Thank you for your answer, i have done what you told me and created two different vqm files for two different modules,however,it is strage that one of the vqm file is full of messy code ,and the other shows normal,why? 

--- Quote End ---  

 

 

Hi, 

 

what kind of modules do you have ? Is one a third party IP block ? 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

Hi, 

 

what kind of modules do you have ? Is one a third party IP block ? 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

hi, 

no,neither of them contains a third party IP block.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

hi, 

no,neither of them contains a third party IP block. 

--- Quote End ---  

 

 

Hi, 

 

is it possible that you post the designfile(s) ? 

 

Kind regrads 

 

GPK
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

hi, 

no,neither of them contains a third party IP block. 

--- Quote End ---  

 

 

hi, 

Does it matter if i use an ip block called sram_16Bit_512k made by Terasic Technologies inc?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

hi, 

Does it matter if i use an ip block called sram_16Bit_512k made by Terasic Technologies inc? 

--- Quote End ---  

 

 

Hi, 

 

I assume that this block is an SRAM-Controller ? That is excatly what mean with an 

third party IP block. Did you get the source of the Controller ? If not , I'm pretty sure that a vqm file of this block will be encrypted.  

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

Hi suplina, 

 

choose : Assignments -> Settings -> Compilation Process Settings ->  

"Save a node-level netlist of the entire design into a persistent source file" 

 

Quartus will create a new directory "atom_netlist". You will find the vqm file in this 

directory. 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

excuse me for jumping in, but what version of Quartus are you using? I'm using 8.1 and I don't see these setting.
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

excuse me for jumping in, but what version of Quartus are you using? I'm using 8.1 and I don't see these setting. 

--- Quote End ---  

 

 

Hi, 

 

which device are you using ? 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

Hi, 

 

which device are you using ? 

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

I'm using cyclone III (e3c780f120), but I understand why it should matter, we are talking about synthesis stage, not about a device feature. :confused:
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

I'm using cyclone III (e3c780f120), but I understand why it should matter, we are talking about synthesis stage, not about a device feature. :confused: 

--- Quote End ---  

 

 

The vqm files are only supported unitl StratixII and CycloneII. The feature is for newer devices disabled. In past vqm files were used e.g. for import of an optimized design into a new project. For newer devices Altera recommends to use the partition flow. 

 

Kind regards 

 

GPK
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Altera_Forum
Honored Contributor II
845 Views

 

--- Quote Start ---  

Hi, 

 

I assume that this block is an SRAM-Controller ? That is excatly what mean with an 

third party IP block. Did you get the source of the Controller ? If not , I'm pretty sure that a vqm file of this block will be encrypted.  

 

Kind regards 

 

GPK 

--- Quote End ---  

 

 

hi, 

i have understood what you mean,thank you for your help.
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