about EPM240 high impedance output

[Altera_Forum]

im now encounter a problem with EPM240 high impedance output,it seems like the io port has connected a low value R to the ground that drop down the voltage provided by other signal on the bus. 

 The circut is very simple.   and the verilog code is: assign aup=adjlevel?1'b0:1'bz; assign bdown=adjlevel?1'b1:1'bz;  aup is connecting to the 485 bus a line with a 3.3k resistor. bdown is connecting to the 485 bus a line with a 3.3k resistor.   my intention is to set aup=1'b0 when adjlevel=1'b1,and aup=1'b1 when adjlevel=1'b0.   but when it is set with aup=1'bz, the EPM240 output pin has change the signal voltage that provided by the 485 bus.(meanning only the output pin,not the 485 a line voltage)    i have try other way by setting the output pin with oc function,but it cant work.   there are no design error in this circuit and it can achieve the desired result The wave form in TDS1k2k_FP.bmp( 2V/DIV ) are the correct performance,but i cant reach this result.........   please help.........

[Altera_Forum]

Without knowing the channel assignments, the states driven to the connected MAX II pins and the external wiring, the oscilloscope waveforms are effectively meaningless. So I can only comment the code. the 1'bz assignments as such can be expected to work unconditionally. But you don't show the complete code, so we can't know, if they are effective at all. 

 As an additional comment, the 3.3V IO of a MAX II isn't suited for usual RS485 levels, unless you can be sure, that all peers are using 3.3V only and the bus don't extend beyond the board boundary. Otherwise damage of the MAX II by overvoltages must be feared.

[Altera_Forum]

i think i havn't got the right answer,maybe i didnt express clearly ,so i send the reference diagram. 

 thanks a lot.........

[Altera_Forum]

is your intension to use the epm pins aup and bdown to enable or disable slightly forced rs485 levels into idle levels ? to enshure proper 0 and 1's when not using the rs485 bus ? 

 your schematic (altium designer?) mentions 5V does this mean your rs485 bus runs at 5v levels between a and b line ?   in addition i fully agree with FvM that you should realy take care about the rs485 levels as the epm240would withstand the emc like a bulletproof 15KV MAX485EESA tranceiver.  between your adlevel 1 -> 0 -> 1 transitions, there seems to be reflection on a and b due to unterminated signals if i interprete these staircases correctly. but what does the blue line mean ? is it the input signal from your tranceiver ?

[Altera_Forum]

--- Quote Start ---  is your intension to use the epm pins aup and bdown to enable or disable slightly forced rs485 levels into idle levels ? to enshure proper 0 and 1's when not using the rs485 bus ?   your schematic (altium designer?) mentions 5V does this mean your rs485 bus runs at 5v levels between a and b line ?    in addition i fully agree with FvM that you should realy take care about the rs485 levels as the epm240would withstand the emc like a bulletproof 15KV MAX485EESA tranceiver.   between your adlevel 1 -> 0 -> 1 transitions, there seems to be reflection on a and b due to unterminated signals if i interprete these staircases correctly. but what does the blue line mean ? is it the input signal from your tranceiver ?  --- Quote End ---       1.is your intension to use the epm pins aup and bdown to enable or disable slightly forced rs485 levels into idle levels ? to enshure proper 0 and 1's when not using the rs485 bus ?   re:Yes, you are so clever.   2.your schematic (altium designer?) mentions 5V does this mean your rs485 bus runs at 5v levels between a and b line ?    re:1.altium designer8.0(hehe...) 2.the voltage supply of 485 ic is 5VDC.But A line and B line DC voltage level is just 2VDC(in the waveform,it's 2 V/div). Rs485 output is 5V TTL,but i have use other convertor which accept 5V TTL and output 3V TTL to make sure the compatible logic level .   3.what does the blue line mean ? is it the input signal from your tranceiver ?   re:Yes,its the input signal.when it represent wide pulse logic 0(excess 80 ns),i will set the epm240 output with logic 0 or logic 1, other case it will set to logic-Z. that is assign aup=adjlevel?1'b0:1'bz; assign bdown=adjlevel?1'b1:1'bz;   but the result is ...............i can Not get the waveform showed as the waveform i have post. it seem like the 1'bz dosn't work,but the adjlevel signal works ok.... -------------------------------------------------

[Altera_Forum]

just to understand you a bit more 

So the green line is A and the violett line is B during adjlevel = 1 A is max 3,3V as this is the EPMs IO voltage and B is 0V A can't reach 5V as the pull up won't be feed with 5V   during adjlevel = 0 A and B are around 2V +/- something so you would expect A and B going from 0V to 3,3V what is not the case and you assume 1'bz not working and the blue signal shows a correct waveform ? 80nsec = 12,5MHz ? that clock should be seen between A and B during 1'bz  wont't you need some termination resistor between A and B ? like 150Ohm or something matching to your cable ?  What about the other side of the RS485 can it drive a 12,5MHz clock ?

[Altera_Forum]

wont't you need some termination resistor between A and B ? like 150Ohm or something matching to your cable ?  

 no neet a termination resistor, cause its just p2p. ---------------------------------- the waveform are right.......... the wrong waveform show as the red lines the attachment with the operation. assign aup=adjlevel?1'b0:1'bz; assign bdown=adjlevel?1'b1:1'bz; --------------------------------------- i think its about the IO resource configuration of MAXII device ,....... ---------------- thanks a lots

[Altera_Forum]

okay green and violett are what you want to have but red is what you get on your implementation ... a bit far away ... 

the red lines might indicate some RC behavioral that it is not fast enough  if it is due to quartus setings, maybe somebody else could help you more but probably would need your project settings (qsf file).

[Altera_Forum]

1'bz means the IO is open circuit to the bus,so the valtage has nothing to do with the IO.You can try on the hardware.

[Altera_Forum]

yes, it means that a tri state buffer is used for the output where adjlevel enables or disables this buffer with a permanent 0 or 1 on its input, but it doesn't say wheter or not some optional bus hold circuit, pull up, clamping diode, ... is added.

[Altera_Forum]

--- Quote Start ---  i think i havn't got the right answer  --- Quote End ---  In my opinion, you didn't manage to tell a clear question. It took three posts to clarify, that you showed expected rather than observed waveforms.  It's not necessary, that we understand the purpose of your circuit (which seems hard to get in terms of RS485 communication practice). We can reduce the discussion to a simple point: You're saying, that the high Z pin setting isn't working. You don't need all the RS485 circuitry and dynamic waveforms to check this. A static measurement should be sufficient. The voltage drop at the 3.3k resistor can tell most exactly, if the pin is sinking a current in the suspected case.