Creating partition issue

[Altera_Forum]

Hi guys: 

  There is a mudule with bidrection pins (inout defined in VHDL) in my design, QII gave out error informations about this module when i created partition for this module.   I refered the QII handbook and didn't find the any restricts about this situation. Do anyone encouter this issue, and how to deal with it?!   Thanks in advance!

[Altera_Forum]

--- Quote Start ---  Hi guys:   There is a mudule with bidrection pins (inout defined in VHDL) in my design, QII gave out error informations about this module when i created partition for this module.   I refered the QII handbook and didn't find the any restricts about this situation. Do anyone encouter this issue, and how to deal with it?!   Thanks in advance!  --- Quote End ---    Hi Jerry,  maybe this is the reason for your problem.  Altera FPGA's do not have internal tristate buffer. The tristate function is replaced by a multiplexer structure by Quartus. The implementation of the muxes will change the interface of your module, but when you define your block as partition Quartus is not allowed to change the interface of the module. The interface of a module in a design partitiion is strictly preserved.  Kind regards  GPK

[Altera_Forum]

Hi pletz: 

 Is it means that block which contains tri IOs can't be defined as a partition?!

[Altera_Forum]

Below is the error information: 

 Error: Net "dataint[15]", which fans out to "HostCom:inst3" is connecting a Partition with logic other than a single Bidirectional pin  Error: Net is fed by "inst3~6"  Error: Net is fed by "CtrlInt:inst1|DataInt[15]"  Error: Net is fed by "CtrlInt:inst1|DataInt[15]"

[Altera_Forum]

--- Quote Start ---  Below is the error information:   Error: Net "dataint[15]", which fans out to "HostCom:inst3" is connecting a Partition with logic other than a single Bidirectional pin  Error: Net is fed by "inst3~6"  Error: Net is fed by "CtrlInt:inst1|DataInt[15]"  Error: Net is fed by "CtrlInt:inst1|DataInt[15]"  --- Quote End ---    Hi Jerry,  I'm not sure, but I think that you can't put a tristate function in a partition. What you should try is, to put the tristate function in a separate module and the remaining part of the design in a partition.   Maybe you can post the design in the forum, so that I could habe look to it.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi Jerry,  I'm not sure, but I think that you can't put a tristate function in a partition. What you should try is, to put the tristate function in a separate module and the remaining part of the design in a partition.   Maybe you can post the design in the forum, so that I could habe look to it.  Kind regards  GPK  --- Quote End ---    Hi Jerry,  I played a little bit with Quartus. I found out that it is not possible to have tristate ports in a partition. Without partition Quartus can covert the tristate ports to a multiplexer structure. If you define one block of your design as design partition Quartus can't do this anymore.   Is the tristate neccessary (?), because it not recommended for FPGA designs. You should change the design description to a multiplexer structure.  I have a small project attached, look into the Tech view to see howw Quartus handles tristates.  Kind regards  GPK

[Altera_Forum]

I think perhaps the best approach is to understand design partitioning and what it is you are asking the tool to do for you. I'm sure you'll find everything you need in the following document and bidirectional pins and internal tri-states are clearly discussed in several places. 

 http://www.altera.com/literature/hb/qts/qts_qii51017.pdf  Have fun, Jake

[Altera_Forum]

--- Quote Start ---  Hi Jerry,   maybe this is the reason for your problem.   Altera FPGA's do not have internal tristate buffer. The tristate function is replaced by a multiplexer structure by Quartus. The implementation of the muxes will change the interface of your module, but when you define your block as partition Quartus is not allowed to change the interface of the module. The interface of a module in a design partitiion is strictly preserved.   Kind regards   GPK  --- Quote End ---       Hi Both，   Thanks for your informaiton. The tri signals are the muc's data bus. I think I only need place the mcu interface in the top level.   thanks again.