Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

50MHz to 1Hz

Altera_Forum
Honored Contributor II
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Hi,I am new planning FPGAs and I need to do a digital clock and I need a frequency of 1Hz. Someone would be able me to say as I obtain this frequency from 50MHz?

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Altera_Forum
Honored Contributor II
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divide it by 50 000 000 

 

Depending on what you want to do with it, it may be a better idea to do a clock enable rather than a new clock signal.
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Altera_Forum
Honored Contributor II
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Use a counter. In your 50MHz clock domain; count to 25,000,000. Each time you reach 25,000,000 toggle your 1Hz clock and reset your counter: 

 

module clk_1( input clk_50mhz, input reset_n, output reg clk_1hz ); reg count; always @(posedge clk_50mhz or negedge reset_n) if(!reset_n) begin count <= 25'd2499999; clk_1hz <= 1'b0; end else begin count <= count + 25'h1ffffff; if(!count) begin count <= 25'd2499999; clk_1hz <= ~clk_1hz; end end endmodule
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