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Floating point pachage

Altera_Forum
Honored Contributor II
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Hi,  

I need to use the Floating-point numbers and i have to compile “fixed_generic_pkg.vhdl” and “fixed_generic_pkg-body.vhdl” first, 

i'm using Quartus II 9.0 (32-bit) 

 

Thank you very much
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Altera_Forum
Honored Contributor II
382 Views

And what is your question or problem ?

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Altera_Forum
Honored Contributor II
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I don't know how to make :confused:

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Altera_Forum
Honored Contributor II
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You dont know how to make what? Do you already have these files or do you need to make them yourself?

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Altera_Forum
Honored Contributor II
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just add them to your project or put the vhdl files in your project folder and they should be compiled ... 

or dont you know how to use the package ? ;p 

 

 

however I dont know whether they are synthesizable because it's vhdl-2008
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Altera_Forum
Honored Contributor II
382 Views

Just realised - the files you mention have nothing to do with floating point. They are fixed point.

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Altera_Forum
Honored Contributor II
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I have already downloaded them from here  

http://www.eda-stds.org/vhdl-200x/vhdl-200x-ft/packages_old/ 

but i don't know how to use these packages in my own project 

 

Thank you very much
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Altera_Forum
Honored Contributor II
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These are the IEEE fixed point packages. They define types and functions that make using fixed point numbers easier in VHDL. There is a similar floating point ppackage, but I wouldnt recommend using it for synthesis. 

 

the fixed point packages mike life alot easier when perforimg mathmatical operations on fixed point: 

 

signal A : ufxied(4 downto -3); --3 bits fractional signal B : ufixed(4 downto -3); -3 bits fractional signal AtB : ufixed(9 downto -6); signal ApB : ufixed(5 downto -3) process(clk) begin if rising_edge(clk) then AtB <= A * B; ApB <= A + B; end if; end process;
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

There is a similar floating point ppackage, but I wouldnt recommend using it for synthesis. 

--- Quote End ---  

I agree. I did a brief test some time ago and it's more a principle demonstration than useful synthesizable code. 

 

Generally, float operation IP has a high resource demand. If a package would be able to infer fp_xxx Megafunctions from your VHDL code, you effectively can't write it down like integer arithmetic. Each instance of float IP has to be well considered. It's often meaningful to use it sequentially for different signals, but of course, this completely changes the structure of your code. 

 

But your above question seems rather to indicate insufficient knowledge of general VHDL concepts, e.g. packages. There's no mistery about it. If you add the package code to your project, it can be compiled. If you add the respective library definitions to your code, you can use the new language elements implemented by the package. As explained, the result won't most likely satisfy you.
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Altera_Forum
Honored Contributor II
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I would take the easy route and start using these: http://www.altera.com/literature/ug/ug_altfp_mfug.pdf?gsa_pos=7&wt.oss_r=1&wt.oss=float Like others have said are you sure you *need* floating point math hardware? In my own experience 80% of the people who think they need it can use fixed point instead.

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