JTAG conflict when debugging dual NiosII system

[Altera_Forum]

We have a dual NiosII arhitecture implemented on a Altera StratixIII dev. kit. The processors only share a dual port ram for communciation, i.e. each (cpuA and cpuB) has its own ram and rom, everything is on-chip for simplicity and reliabilty. 

 We debug the software using EclipseIDE. We can download and debug each of the processors but only one at a time. If we download and debug cpuA and then start download and debug of cpuB (or vice versa) we get the console message "another application is using the target processor (or is using the jtag cable in a way which conflicts with our request to use the target processor). please close down that application and try again."   And in the debug window the last to load has the annotation: <terminated> appcpub [nios ii hardware] <terminated,exit value: 8> nios ii download output (date)   We have ticked ON the tick mark "window->preferences->nios ii->allow multiple active run/debug sessions" In the debug configuration we have in the "jtag device": marked as "automatic <the device which has the processor>"   In another thread (from 2004!) "http://www.alteraforum.com/forum/showthread.php?t=13002&gsa_pos=1&wt.oss_r=1&wt.oss=debug multi nios" Kerri mentions the requirement to supply a unique "tcp port for debugger" but there is no such option in the debugger tab in IDE Q9.1. I am wondering if the problems we face could be due to a deficiency in the USB-blaster which is built-in to the StratixIII dev kit, and as such could be different from the stand-alone USB-blaster normally used in at least older dev kits and thus extensively tested? Edit: [I have reconfigured the board to use a standalone Byte-blaster. This changes nothing, so the programmer is not the cause]   We have now struggled for days with this trying to get through, by debugging only one cpu at a time but it is not working very well, so we hope someone has a hint or two. regards Henning

[Altera_Forum]

Make sure to load the .jdi file for each application project before debugging the code. This will make sure the debugger knows which processor debug module is being targeted. It could be that the IDE is trying to attach to the debugger of the wrong CPU. The load .jdi file is in the 2nd 'debug as' menu. 

 Each debugger will have a unique instance ID which is how the tools distinguish the various JTAG IP that you have in the FPGA. Search for "JTAG" in this document and you'll find out a little bit more about this.  http://www.altera.com/literature/hb/nios2/edh_ed_handbook.pdf

[Altera_Forum]

--- Quote Start ---  Make sure to load the .jdi file for each application project before debugging the code.   --- Quote End ---   spot on! Thanks a lot.