Master reset and nconfig

[Altera_Forum]

Hi, 

 We have a deisgn with iMx27 and 3 cyclones. The 3 have their FPP configuration pins connected to the iMX. During power on reset, the iMX has to hold low the 3 FPGAs until is ready to send configurations to these FPGA one at a time. We have another reset signal coming from the mother board, is used to reset the iMX27 and other parts on the board. Do need to reset the FPGA at nconfig with this reset signal? How will be the status of the FPGAs in this time when the iMX receives this global reset?  Thanks  MJ

[Altera_Forum]

As soon as nCONFIG is low the FPGA will enter configuration mode. 

All pins will be tristate, execpt those used for configuration.  So if your external reset signal enshures that all FPGAs nCONFIG will be 0 then you should be on a safe side.  If you need to route the external reset to nCONFIG (in any kind) depends upon your application if you want to have your FPGA in a well known safe state or if you want to keep them doing their job until they get reconfigured.  Regards.

[Altera_Forum]

Thanks a lot for your quick answer. How about nSTATUS signal in FPP where the POR time is between 3 to 9ms; do the iMX needs to pulled it low for the time of boot (I mean before configuration)? or the FPGA can be left in this stage waiting for the configuration to start by iMX without controlling any config pins?:confused: 

 Thanks  MJ