encoutered a confusing prob. about its warning

[Altera_Forum]

I got a warning :"input pins that donot drive logic".In my project I use a "component" sentence. The problem is when I compile the component only ,that input pin xx work(the warning disappear,I can see its route),but when I connect it to upper structure, it show up.So who tell me why? Or why it was synthesized away while be used as a component?Thanks!

[Altera_Forum]

The problem is surely caused by missing connectivity of the component in the full design. Missing clock, component held inadvertently in permanent reset or no design output depending on the respective component are possible reasons. 

 Please consider, that minimization of logic is an important feature of a design compiler. Unfortunately it also allows you to remove your complete design logic by omitting just one signal connection.

[Altera_Forum]

I guess, that reading the warnings strictly can help you to see, where design connectivity is missing. Tracing the signal flow is my usual method. If it all doesn't help, you have still a last resort of adding auxilary in- and output signals to your design to span part of the signal flow.

[Altera_Forum]

Thanks,but I haven't found any missing connections,does this case that component's output are stuck at '0' cause the input pin synthesized away?

[Altera_Forum]

I cann't assemble any until now.The connetcion was there when seen in RTL ,but lost in techology map viewer. This maybe mean that it is not because the connection that I neglect,but the fitter or synthesis's judgement for that model output of that input pin always stuck at GND ,known from warning,so they just omit their input pin's connection. Anyone here have better ideas?

[Altera_Forum]

--- Quote Start ---  I cann't assemble any until now.The connetcion was there when seen in RTL ,but lost in techology map viewer. This maybe mean that it is not because the connection that I neglect,but the fitter or synthesis's judgement for that model output of that input pin always stuck at GND ,known from warning,so they just omit their input pin's connection. Anyone here have better ideas?  --- Quote End ---    Hi ,  define your component as design partition. This will preserve the IF of the component. If the root cause of the problem is in the block driving the component, you should see which signal(s) are tied to VCC or ground .  Kind regards  GPK

[Altera_Forum]

Which implies there is a problem in your code, not with the synthesis tool. 

 Have you tried running this code in a simulator?

[Altera_Forum]

I have simulated it modelsim in whose testbench I assigned the unconnected input pin,,but its output always stuck at GND. So I looked at the techology map viewer finding that one input pin didnot has its connection.Thanks for all of you. You are kind hearted!Bless