Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

speed grade

Altera_Forum
Honored Contributor II
974 Views

Hi; 

Now,I am designing a production with Cyclone III.But I don't understand what is speed grade.In the datasheet,block RAM can be designed up to 315MHz,then is it up to the max speed for the lowest speed device?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
233 Views

See Table 1-22 in this pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii5v2_01.pdf). 315 Mhz, 274 MHz, and 238 MHz for speed grades 6, 7, and 8, respectively.

0 Kudos
Reply