Imported partition(QXP) Fmax question

[Altera_Forum]

I'm synthesizing a design using a bottom up flow where a top partition imports previously generated and exported lower partitions. However, the top level Fmax reported by Quartus is lower than the Fmax for the imported lower partition.  

 For example: Quartus reports that partition_A has an Fmax of 30MHz for clock_A. In this case clock_A is only used in partition_A. However, after importing partition_A while preserving placement and routing and building a top level, Quartus reports that clock_A in the top level has an Fmax of 25MHz.  Any thoughts on why I'm losing 5MHz of Fmax after partition import?

[Altera_Forum]

--- Quote Start ---  I'm synthesizing a design using a bottom up flow where a top partition imports previously generated and exported lower partitions. However, the top level Fmax reported by Quartus is lower than the Fmax for the imported lower partition.   For example: Quartus reports that partition_A has an Fmax of 30MHz for clock_A. In this case clock_A is only used in partition_A. However, after importing partition_A while preserving placement and routing and building a top level, Quartus reports that clock_A in the top level has an Fmax of 25MHz.  Any thoughts on why I'm losing 5MHz of Fmax after partition import?  --- Quote End ---    Hi,  maybe you have now a longer path to or from your design partition to other modules in your design. Do you have registers at your inputs and outputs of your partition ?  Kind Regards  GPK

[Altera_Forum]

pletz, 

 Thank you for your reply.   I have registered all inputs and outputs to the partition. However, in this case, the clock domain in question is entirely internal to the partition. It is an isolated clock island within the partition with all inputs and outputs passing through retiming logic.

[Altera_Forum]

--- Quote Start ---  pletz,  Thank you for your reply.   I have registered all inputs and outputs to the partition. However, in this case, the clock domain in question is entirely internal to the partition. It is an isolated clock island within the partition with all inputs and outputs passing through retiming logic.  --- Quote End ---    Hi,  maybe a stupid question, did you check that the setting is for "Fitter Preservation Level" is set to "Placement and Routing". I'm not sure, but is the LL also impotrted ?  Maybe other clock routing ????  Kind regards  GPK

[Altera_Forum]

Yes, I checked that the "Fitter Preservation Level" is 

set to "Placement and Routing".   What is LL?  What other clock routing do you mean? Does Quartus change the clock routing after importing a partition?

[Altera_Forum]

--- Quote Start ---  Yes, I checked that the "Fitter Preservation Level" is set to "Placement and Routing".   What is LL?  What other clock routing do you mean? Does Quartus change the clock routing after importing a partition?  --- Quote End ---    Sorry, LL means LogicLock region.  I'm not sure, but I expect that the routing to the clock input of the partition will be different.   Kind regards  GPK