- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Can you tell me why im getting these errors for this code:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY DAC2 IS PORT( hardwarecontrol: IN STD_LOGIC; -- Control Hardware Shut Down input: IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- Input Value for sine wave clock: IN STD_LOGIC; -- Clock Input from Altera Board cs: OUT STD_LOGIC; -- Chip Select sck: OUT STD_LOGIC; -- Serial Clock Input sdi: OUT STD_LOGIC; -- Serial Data Input ldac: OUT STD_LOGIC; -- Latch DAC Input shdn: OUT STD_LOGIC -- Hardware Shutdown Input ); END DAC2; ARCHITECTURE behaviour OF DAC2 IS SIGNAL count: STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN sck <= clock; IF RISING_EDGE(clock) THEN IF (hardwarecontrol = '1') THEN cs <= '0'; ldac <= '1'; PROCESS(clock,input) BEGIN IF (count = "0000") THEN sdi <= '0'; ELSIF (count = "0001") THEN sdi <= '1'; ELSIF (count = "0010") THEN sdi <= '0'; ELSIF (count = "0011") THEN sdi <= '1'; ELSIF (count = "0100") THEN sdi <= input(11); ELSIF (count = "0101") THEN sdi <= input(10); ELSIF (count = "0110") THEN sdi <= input(9); ELSIF (count = "0111") THEN sdi <= input(8); ELSIF (count = "1000") THEN sdi <= input(7); ELSIF (count = "1001") THEN sdi <= input(6); ELSIF (count = "1010") THEN sdi <= input(5); ELSIF (count = "1011") THEN sdi <= input(4); ELSIF (count = "1100") THEN sdi <= input(3); ELSIF (count = "1101") THEN sdi <= input(2); ELSIF (count = "1110") THEN sdi <= input(1); ELSIF (count = "1111") THEN sdi <= input(0); cs <= '1'; ldac <= '0'; shdn <= '1'; END IF; count <= count +1; END PROCESS; ELSIF (hardwarecontrol = '0') THEN count <= "0000"; END IF; END IF; END behaviour; Error (10500): VHDL syntax error at DAC2.vhd(26) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at DAC2.vhd(26) near text "THEN"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at DAC2.vhd(27) near text "THEN"; expecting "<=" Error (10500): VHDL syntax error at DAC2.vhd(85) near text "ELSIF"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at DAC2.vhd(85) near text "THEN"; expecting "<=" Error (10500): VHDL syntax error at DAC2.vhd(87) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architectureLink Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Changed as below: PROCESS(clock,input) BEGIN IF RISING_EDGE(clock) THEN IF (hardwarecontrol = '1') THEN cs <= '0'; ldac <= '1'; IF (count = "0000") THEN sdi <= '0'; ELSIF (count = "0001") THEN sdi <= '1'; ELSIF (count = "0010") THEN sdi <= '0'; ELSIF (count = "0011") THEN sdi <= '1'; ELSIF (count = "0100") THEN sdi <= input(11); ELSIF (count = "0101") THEN sdi <= input(10); ELSIF (count = "0110") THEN sdi <= input(9); ELSIF (count = "0111") THEN sdi <= input(8); ELSIF (count = "1000") THEN sdi <= input(7); ELSIF (count = "1001") THEN sdi <= input(6); ELSIF (count = "1010") THEN sdi <= input(5); ELSIF (count = "1011") THEN sdi <= input(4); ELSIF (count = "1100") THEN sdi <= input(3); ELSIF (count = "1101") THEN sdi <= input(2); ELSIF (count = "1110") THEN sdi <= input(1); ELSIF (count = "1111") THEN sdi <= input(0); cs <= '1'; ldac <= '0'; shdn <= '1'; END IF; count <= count +1; ELSIF (hardwarecontrol = '0') THEN count <= "0000"; END IF; END IF; END PROCESS;- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hey, thanks a lot. So you pulled the end process outside the elsif hardwarecontrol? But i began the process inside the if hardwarecontrol=1 statement. Does this matter?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Does this matter? --- Quote End --- Yes. It's against the law (respectively VHDL syntax rules). It seems like you didn't understand the concept of VHDL processes. I suggest a VHDL text book.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
So it's not possible to start the process in an if statement?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- So it's not possible to start the process in an if statement? --- Quote End --- No. Procedural code (including if statements) have to go inside a process. Processes define code to be "executed" if any of the signals in the sensitivity list change. Outside of a process you can only have single signal assignments that are generated from combinatorial logic.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
As another point - a process cannot be started at will. Processes ALWAYS run, and all of them run in parrallel. You can have a process wait, but you can never stop or start it.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
O ok, thanks. Now I guess my question is, will this do what I want it to? I am trying to write the input information to the date input of a dac on bit per clock cycle.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Also, does anyone know why I cant compile on my home version of Quartus ii?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
In my opinion, the bit selection by a chain of if statements looks awful, although the design compiler can reduce it. Generally a shift register is the ususal way to generate a serial bitstream. See the code example in another thread related to SPI output.
http://www.alteraforum.com/forum/showthread.php?t=19729 "why I can't compile" is too unspecific to answer, I think.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hmm, thanks for the example. I am somewhat short on time though, so if my code will work then I will use it. Also I mean, I literally cant start compiling, the program wont give me that option for some reason.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hello everyone...
can anyone tell me whats wrong wif diz code? component RAM is generic (K, W: integer); -- number of address and data bits port (WR: in std_logic); -- active high write enable ADDR : in std_logic_vector (W-1 downto 0); -- RAM address DIN: in std_logic_vector (K-1 downto 0); -- write data DOUT: out std_logic_vector (K-1 downto 0); -- read data end component RAM; i new with vhdl, i now working my final year project using vhld, so i in learning process. this code give me error 10500 "Error (10500): VHDL syntax error at fifo.vhd(25) near text "ADDR"; expecting "end"" TQVM in advance...- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
you need to put the ports inside the ()
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page