I meet some problems when using sopc builder

[Altera_Forum]

I use stratix s10f780c6 nios develop kit. use board_setting.tcl which contant in standard verilog example to assign pins.if i use ext_sram,then: 

Error: Can't place node ~DATA0~ in location H12 because location already occupied by node data_to_and_from_the_sram[0] Error: Can't fit design in device Error: Quartus II Fitter was unsuccessful. 2 errors, 29 warnings  Error: Peak virtual memory: 195 megabytes  Error: Processing ended: Thu Nov 26 15:50:18 2009  Error: Elapsed time: 00:00:06  Error: Total CPU time (on all processors): 00:00:05 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 337 warnings   if i not use ext_sram then quartus II display i download the *.sof succed.but nios eds display that: There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.   why?how could i avoid those problems?

[Altera_Forum]

--- Quote Start ---  Error: Can't place node ~DATA0~ in location H12 because location already occupied by node data_to_and_from_the_sram[0]   --- Quote End ---   without knowing the exact details of this dev kit, i would suspect that there is a conflict in the configuration mode and/or dual-purpose pins. But double check the datasheet for the dev kit if the pinout for ....sram[0] is correct. DATA0@H12 is correct!   Go to Assignments->Device->Device->Device and pin options->Configuration or Assignments->Device->Device->Device and pin options->Dual-Purpose Pins. There are some pins for configuration DATA[7..0].  This bug - wrong configuration scheme as well as unfortunate drive property of unused pins is very easy to stumble on. The latter can be damaging to you FPGA and/or your peripheral if you have a drive conflict. During development I always use either "As input tristate with pullup" or "as input with bushold", but you should avoid the other options: 1) bare input - for noise reasons and 2) drive low/High for short circuit reasons. In a consolidated design you can think of driving the unused pins to give better immunity. Drive property of unused pins you also setup in the same area Assignments->Device->Device->Device and pin options->Unused pins.