Pushing standard serial comm protocol (aka UART) past 1-2Mbps is usually problematic. Transmitting data at that rate is not a problem, but you need to have some logic on the receive side that can recover the data error free, and most PC UARTs won't run reliably past about 1Mbps or so.
USB 2.0 could do the data rate, but USB has a high protocol and implementation overhead (much more complex than a UART). You would also need (most likely) an external USB PHY as most FPGA pins can't do the USB signaling directly.
Using a SPI interface is pretty simple (clock, data out, data in, select) and could easily run at 10-40Mbps in a FPGA using standard LVCMOS I/O. But then it requires whatever you connect to be able to process the SPI signaling protocol.
I suspect you just want to run a cable from your logic and connect it to a bog standard Windows PC, so this would then limit your options to (probably) serial UART via an external USB-serial adapter, limiting you to somewhere in the range of 1-2Mbps at most.
Of course if your FPGA and support board have an etherNet PHY you could always send the data over etherNet at 100Mbps, but this is a much more complicated solution on your FPGA side.
