Good progress on UART

[Altera_Forum]

I have my Uart Working, but not perfectly, GPGGA comes from the GPS chip once a second, about every 5 seconds my UART reads it perfeclty giving my Time and position, any sugestions how to fine tune this? 

 //working under 27mhz clock, Buad rate it 9600, 1 start bit, docs do not indicate stop bit  if (bitcount!=0) bitlength=2812; if (bitcount==0) bitlength=3800;   if (uartf==0 & GPSIN==0)   begin  uartf<=1;  bitstreamin<=0;  bitcount<=0;  bitqueu<=bitqueu << 8;  // shifting queu left 8 bits to make space for new byte  end   if (uartf==1) begin   if (bittimer!=bitlength) bittimer<=bittimer+1;  if (bittimer==bitlength)  begin  // bitstreamin[10]<=bitstreamin[9];  bitstreamin[9]<=bitstreamin[8];  bitstreamin[8]<=bitstreamin[7];  bitstreamin[7]<=bitstreamin[6];  bitstreamin[6]<=bitstreamin[5];  bitstreamin[5]<=bitstreamin[4];  bitstreamin[4]<=bitstreamin[3];  bitstreamin[3]<=bitstreamin[2];  bitstreamin[2]<=bitstreamin[1];  bitstreamin[1]<=bitstreamin[0];  bitstreamin[0]<=GPSIN;  bittimer<=0;  bitcount<=bitcount+1;  end  if (bitcount==9)  begin  uartf<=0;  bitcount<=0;   bitqueu[0]<=bitstreamin[8];  bitqueu[1]<=bitstreamin[7];  bitqueu[2]<=bitstreamin[6];  bitqueu[3]<=bitstreamin[5];  bitqueu[4]<=bitstreamin[4];  bitqueu[5]<=bitstreamin[3];  bitqueu[6]<=bitstreamin[2];  bitqueu[7]<=bitstreamin[1];    end   end   // gpsdecode(bitstreamin,charcount,latitude,longitude,gpstime)    /// ascii "$"=24h "A"=41h "G"=47h "P"=50h "A"=41h  //   //$GPGGA asci hex = 244750474741  //$GPGGA,hhmmss.ss,llll.lll,a,nnnnn.nnn,b,t,uu,  // Active low GPSIN (PDFLINK ABOVE FOR GPS MODULE)  // LED TO PPS PIN SHOWS GPS properly powered  // $GP ascii=2447h  // hits to this per second  if (bitqueu[447:400]==48'h244750474741)   begin  secsmain<=secsmain+1;  gpstream<=bitqueu;  bitqueu<=0;  end     mLEDR<=rledt; end //posedge clock27

[Altera_Forum]

I don't see a clear reason for frequent receive failure, some problems exist however: 

- GPSIN must be registered for a reliable startbit detection. - bittimer should be reset on start  Usually, an UART would start with a bittimer period of a half bit length and immediately reset the receiver if an invalid start bit (e.g. an input glitch) is detected. I also don't understand the motivation for the 1.35 bit length timer interval, but it should work anyway.  NMEA standard specifies 8,N,1 frame, it can be expected for your GPS device as well.  As a general comment, the Verilog language knows various constructs to write the bitshifts more compact, e.g. as a for loop or a concatenation. I would also prefer an array of bytes for the output data. Although Verilog is somewhat limited in representing data structures, it can do better.  To understand, why the design receives many telegrams incorrectly, I suggest SignalTap.

[Altera_Forum]

I suspect I may be getting seperates bytes correctly, and then glitching on consecutive bytes by missing the second byte. My program has the time part of the $GPGGA string on the text LCD. and it reads like 

060715. 060717. 060720. 06072. 060722 06725 This might be why I can detect $GPGGA every 3 seconds or so, and get a few garbled latitude longitude string.I will continue with that signal tap idea.

[Altera_Forum]

Hi, I am currently working on a similar project for school using the Copernicus GPS module and a FPGA. I have been trying to write verilog code to implement a UART for transmission between the two. I have been unsuccessful at acquiring the data with my code and uart models available online. I'm not sure what I am doing wrong. I was wondering since you got your uart working if you could give me a hand. Would you be willing to explain how you accomplished the uart with pseudo code? or by giving me an example. It's hard to tell exactly whats going on in your code by only looking a snippets. I just want to be able to read the data with the FPGA. Thanks! I'm looking forward to hearing from you and making some progress!

[Altera_Forum]

It runs off a 27mhz clock, it assumes until a byte is coming in the signal is high, then goes low when the startbit comes in. 

uartf is the uart flag, which goes high when byte start to come in, it counts 3800 clock ticks to skip the start bit and pick up the first data bit, then every 2812 ticks it grabs another bit until its gets all 8. bitstreamin[9]<=bitstreamin[8]; bitstreamin[8]<=bitstreamin[7]; bitstreamin[7]<=bitstreamin[6]; bitstreamin[6]<=bitstreamin[5]; .........................................  When the 8 bits are in, the second part puts the byte on the bitqueu, shifting the bitquee by 8 bits to make room for the new byte bitqueu<=bitqueu << 8; // shifting queu left 8 bits to make space for new byte  I started this project with a copernicus breakout board I got from Sparkfun that one night just quit on me, to use this code you would have to recalcuate the bitcounts, the Copernicus use 4800 bits per second (baud), the Venus one I am using now uses 9600 baud.  I have this kind of working, but it needs more work after I finish my PCB design. Please let me know if you try my code, Im curious if you get fewer glitches then me.

[Altera_Forum]

There is a N81 uart available in "communication" directory of the altera cookbook for Statix ii devices (but it also works with others). Just search the altera website for "cookbook" and download the .zip file.

[Altera_Forum]

I need your help to figure out how to connect the PC RS232 to the NIOS UART on a C III starter board. I have a daughter card that exposes the FPGA pins, so I have access physically to ALL I/O pins, Also 5 V and 3.3 V pins on that card. I also have a RS232 to TTL tiny external board that is connected to the PC Serial cable, and has 4 pins as output. The four pins are Power, GND, Tx and Rx. I tried to connect the Tx and Rx to their perspective equal Rx and Tx in the NIOS (pin assignment is correct) after I added the RS232 UART in the nios using SOPC builder, with no flow control. 

 I cannot send or receive on either sides, I mean Nios running c code cannot read or write, the function call stuck. Also on the PC the c code cannot read or write it does also stuck on the function call.  I am using ANSI standard C code for fopen, fgetc, fputc, etc..  Can you help me please to find out how to connect the PC to the UART on the FPGA?  I appreciate it. Thanks.