Video and Image Processing Suite for DE_70

[Altera_Forum]

Hi! 

 I'm interested in "Video and Image processing Suite (VIP)" cores for DE2-70 development board. I'm trying to adapte "video sync generator" core to IC named "ADV7123" for VGA out. I think that the settings for "video sync generator" core must be 640*480 px and 24 Bits DataWidth and 1 Beat Per Pixel.   These are my questions   1- How can I connect the "Test Pattern Generator" core and "video sync generator" core with 24 Bits DataWidth and 1 Beat Per Pixel? 2- How can I connect the "video sync generator" core to "ADV7123" IC?   ( DEN , HD , RGB_OUT , VD ) <=???=> ( VGA_BLANK , VGA_B , VGA_G , VGA_HS , VGA_R , VGA_SYNC , VGA_VS )

[Altera_Forum]

I don't think the Video Sync Generator is intended to be used with the VIP suite cores. This is why they are not listed together in the same category in SOPC builder. 

 Instead, you should take a look at the Clocked Video Output core from VIP. This core outputs the video sync signals as well as the video data.

[Altera_Forum]

I didn't know that the function of the "video sync generator" could be done by using "clocked video output" then I have tried to work with "clocked video output". I set the "clocked video output" as 640*480 pixels and 8 bit x 3 parallel colour. I tied up the sopc clock, oVGA_CLOCK and vid_clk_to_the_alt_vip_itc_0 25 Mhz signal. I am not sure if the connection between "clocked video output" and the adv7123 integrated circuit is correct and I didn't get any image.How should I adjust the settings of "clocked video output" and values of the clock resources and connections "clocked video output"<=>adv7123 to make it work? 

(underflow_from_the_alt_vip_itc_0, vid_clk_to_the_alt_vip_itc_0,  vid_data_from_the_alt_vip_itc_0, vid_datavalid_from_the_alt_vip_itc_0,  vid_f_from_the_alt_vip_itc_0, vid_h_from_the_alt_vip_itc_0,  vid_h_sync_from_the_alt_vip_itc_0, vid_v_from_the_alt_vip_itc_0,  vid_v_sync_from_the_alt_vip_itc_0)<=> ( VGA_BLANK , VGA_B , VGA_G , VGA_HS , VGA_R , VGA_SYNC , VGA_VS ) http://img109.imageshack.us/img109/1795/clockedvideooutput.th.jpg (http://img109.imageshack.us/i/clockedvideooutput.jpg/) http://yfrog.com/31clockedvideooutputj  http://www.alteraforum.com/forum/C:%5CUsers%5Cspeak%5CDesktop%5Cclocked%20video%20output.jpg

[Altera_Forum]

I am not familiar with the DE2-70 or the ADV7123, so I can't really help much with the details there. 

 On the timings bit, I might be able to help. I have successfully used these timings for 640x480 before: H sync - 96 H front porch - 16 H back porch - 48 V sync - 2 V front portch - 10 V back porch - 33

[Altera_Forum]

Thanks for your answer. I've realized timing values and changed them yesterday. I've maked up the connections and got color bar. ;)

[Altera_Forum]

can you please decribe the connection you made? 

I mean from the fpga to the digital to analog converter and the vga HS & VS.

[Altera_Forum]

of course. I made clocked video core work but then I wasn't able to make sgdma core work properly.It shows white colour only when I make whole screen white.It doesn't show other colours.clocked video output adv7123 connections are shown below:  

 assign oVGA_CLOCK=iCLK_25; assign oVGA_SYNC_N=1'b0; assign oVGA_R[1:0]=2'b00; assign oVGA_G[1:0]=2'b00; assign oVGA_B[1:0]=2'b00;  .underflow_from_the_vga(), .vid_clk_to_the_vga(oVGA_CLOCK), .vid_data_from_the_vga({oVGA_R[9:2],oVGA_G[9:2],oVGA_B[9:2]}), .vid_datavalid_from_the_vga(oVGA_BLANK_N), .vid_f_from_the_vga(), .vid_h_from_the_vga(), .vid_h_sync_from_the_vga(oVGA_HS), .vid_v_from_the_vga(), .vid_v_sync_from_the_vga(oVGA_VS),

[Altera_Forum]

Oh...... interesting... 

 i hadn't though about!  thank you fot the post!

[Altera_Forum]

--- Quote Start ---  of course. I made clocked video core work but then I wasn't able to make sgdma core work properly.It shows white colour only when I make whole screen white.It doesn't show other colours.clocked video output adv7123 connections are shown below:    assign oVGA_CLOCK=iCLK_25; assign oVGA_SYNC_N=1'b0; assign oVGA_R[1:0]=2'b00; assign oVGA_G[1:0]=2'b00; assign oVGA_B[1:0]=2'b00;   .underflow_from_the_vga(), .vid_clk_to_the_vga(oVGA_CLOCK), .vid_data_from_the_vga({oVGA_R[9:2],oVGA_G[9:2],oVGA_B[9:2]}), .vid_datavalid_from_the_vga(oVGA_BLANK_N), .vid_f_from_the_vga(), .vid_h_from_the_vga(), .vid_h_sync_from_the_vga(oVGA_HS), .vid_v_from_the_vga(), .vid_v_sync_from_the_vga(oVGA_VS),  --- Quote End ---     Thank you!

[Altera_Forum]

now I am trying to build vga signal by using sgdma and clocked video output. when I connected "test pattern generator" to the "clocked video output", it was working properly but when I connect sgdma, it shows the image as about 33-35 pixel shifted up. why does this shifting problem occur?and how can I solve it? 

with a code as follows, I can send r,g,b colours to whole screen and it can refresh the screen 3 times in a second (3 fps). what kind of real time video can I play using this performance?  ... alt_video_display * vga; vga=alt_video_display_init("/dev/sgdma",640,480,32,SSRAM_BASE,DESCRIPTOR_MEMORY_BASE,1); ... for(p=0;p<10;p++){ for(x=1;x<=480;x++){ for(y=1;y<=640;y++){ vid_set_pixel(y,x,0xff,vga); } } for(x=1;x<=480;x++){ for(y=1;y<=640;y++){ vid_set_pixel(y,x,0xff00,vga); } } for(x=1;x<=480;x++){ for(y=1;y<=640;y++){ vid_set_pixel(y,x,0xff0000,vga); } } } ... http://img163.imageshack.us/img163/7116/sgdmacvo.th.jpg (http://img163.imageshack.us/i/sgdmacvo.jpg/)

[Altera_Forum]

Hi speak48 Could u upload the pictures again, I need to check how you connected the two Ip cores. please if you can give me more details about these Ip cores, I don't know if they're installed in my sopc system or not. 

thanks