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You could just post your homework assignment for us. :)
You could create a task that contains your loop. Then just schedule the task to run at some predefined interval. Jake- Mark as New
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Hi Jakob,
I wish this was only an assignment :) I do thank you though and if you do have any other suggestions please do let me know. thanks- Mark as New
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I presume you are aware of the $stop and $finish directives in verilog?
Descriptions from the sutherland HDL reference: $finish; Finishes a simulation and exits the simulation process. $stop; Halts a simulation and enters an interactive debug mode. Jake- Mark as New
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thanks for your help..
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This should make modelsim get stuck in an infinite loop in VHDL:
signal a : std_logic := '1';
signal b : std_logic := '0';
...
b <= a and not b;
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thanks tricky... did end up doing something like that. general question can anyone give me an example how do i make 2 always loops to be continuously switching between each other
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you can try
... process begin ...... loop wait until clk='1'; ...... end loop; end process;- Mark as New
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Did I conceive a circuit under quartusII and do I want validated it by a file of data to elaborate by a program in C language, and to recover the exits as a file text, how to make?
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