problem with vedio process using VIP

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

problem with vedio process using VIP

930 Views

hi everyone ,

i am using SOPC IP to process image ,my project flow is

PAL image--->ADV7189(YCbCr)--->Clocked video input--->clocked video output--->ADV7123(RGB),now i have not been make image display successfully.the display screen is all black.following is my problem:

1.can the clocked video input connect the clocked video output directly?

2.how can i connect the clocked video output signal(vid_data_from_the alt_vip_itc_0,vid_datavalid_from_the alt_vip_itc_0,vid_trs_from_the alt_vip_itc_0 and so on ) with ADV7123 signal(DAC_DATA[9:0],CYSNC,CBLANK,CCLK)?

if anyone can help me ,thank you!

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.