Register Chaining with minimal resources

[Altera_Forum]

I am looking to create a register chain that does not use any LUT inputs in an LE as well as not taking an routing resources within a LAB except for the input and output. Meaning, that the connection between LEs within a LAB is done with the "Register Chain Routing From Previous LE" as described in the Device Handbook of most Cyclone and Stratix devises.  

 I have attempted this using LPM, WYSIWYG primitives, and altera generic primitives. These have always used LOCAL_LINE or LOCAL_INTERCONNECT resources. The do, however, avoid using LUT inputs. How do I force the tools to use this special register chain? I have even introduced manual placement constraints to force each bit in my register chain to follow each other physically. Below are my placement constraints:  set_location_assignment LCFF_X94_Y4_N1 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N3 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N5 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N7 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N9 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N11 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N13 -to "regchain2:thechain|regscan:comb_3|chain" set_location_assignment LCFF_X94_Y4_N15 -to "regchain2:thechain|regscan:comb_3|chain"  Attached is my design file (Verilog) for generating a register chain using altera primitives. Also attached is the generated VQM file of the design for reference.  https://www.alteraforum.com/forum/attachment.php?attachmentid=2019  https://www.alteraforum.com/forum/attachment.php?attachmentid=2020   Thanks,  Peter

[Altera_Forum]

The register chain connection feature is connecting DFF.Q to next DFF.D. Your regscan_gen.v is connecting Q to ASDATA. Apart from the fact, that many recent FPGA families don't have an ASDATA port at all, they surely don't provide fast chaining - because there's no reasonable application for it.

[Altera_Forum]

Note that when a LUT is used as a pass-thru(i.e. it's not doing logic, it's just used to get to the FF), it's done by the router, and is not a physical structure that gets synthesized or affects placement. This is often done because it provides flexibility to the router and in many architectures, there is a pass thru the LUT that is actually faster than bypassing it. All of these are good things, they just make it hard to control. One thought might be to put a super-fast timing constraint between the registes, i.e. something like: 

set_max_delay -from {*|chain[*]} -to {*|chain[*]} 0.5 That might get it to use the connection you want, but I'm not sure. Can you explain why you're trying to do this? Part of the reason it's not easy to do is that there's generally not a reason to force something like this. (I'm not saying you don't have a good reason, just that it's not something necessary in most designs and therefore not something that gets asked for.)

[Altera_Forum]

Well, eventually I would like to use the LUT for an arbitrary function as well as the scan chain to read out the values of the function results. This may seem too tedious, but it has a greater purpose, I promise. This is why I used the .sdata input for the scan chain, so I could use the .d input for the LUT result.

[Altera_Forum]

But since the connection is done by the router, if you put in logic that uses the LUT, then the router won't use it for a connection. I don't think you have to pro-actively avoid it.

[Altera_Forum]

I guess the issue is the fact that I need to switch between the LUT output and the register chain from the previous ff. If I put a mux statement in the code, I assume it will use LUT resources to implement this mux. I want to see if I can use the build in "mux" that must be there when I use the .sload port in combination with the .sdata port. Thanks for your input.