unable to display state transition due to long processing time

[Altera_Forum]

i'm trying to work with the FSM viewer on a program that contains only 3 states and all i got is :"unable to display state transition due to long processing time"  

i cant figure out what is the problem ??   maybe somone got a clue ??  the program is :   LIBRARY ieee; USE ieee.std_logic_1164.all;  -- Entity Declaration ENTITY Baud_Rate IS  -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!  PORT  (  Ser_Data : IN STD_LOGIC;  Reset : IN STD_LOGIC;  Clk : IN STD_LOGIC;  Baud_Rate_Clk : OUT STD_LOGIC  );  -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!   END Baud_Rate;  -- Architecture Body ARCHITECTURE Baud_Rate_architecture OF Baud_Rate IS TYPE State IS (Initial,First_Bit, Baud_Calc,Jump,Next_Pkg,Sample,Output_Clk); SIGNAL Cur_State : State; BEGIN PROCESS (Clk,Reset,Ser_Data) ------------------------------Initialization Of Variables -------------------------------- VARIABLE Int_Clk: INTEGER RANGE 0 TO 50000 :=0; VARIABLE Ticks_Count : INTEGER RANGE 0 TO 50000 :=0; VARIABLE Bit_Count : INTEGER RANGE 0 TO 50000 :=0; BEGIN  IF (Reset='0') THEN   Baud_Rate_Clk<='0';  Int_Clk:=0;  Ticks_Count:=0;  Bit_Count:=0;  Cur_State <=Initial; ELSIF ( clk'EVENT AND clk='0') THEN   CASE Cur_State IS   ------------------ Variable Initializations And 'Start' Acceptence -------------------------   WHEN Initial=>  Int_Clk:=0;  Ticks_Count:=0;  Bit_Count:=0;  IF (Ser_Data='0') THEN   Cur_State <=First_Bit;  else Cur_State <=Initial;  END IF;  ------------------- First Bit Acceptence ------------------------------------------------   WHEN First_Bit=>   Int_Clk:=0;  Ticks_Count:=0;  Bit_Count:=0;   IF (Ser_Data='1') THEN   Cur_State <=Baud_Calc;  END IF;     ---------------------- Baud Rate Calculation ------------------------------------   WHEN Baud_Calc =>   IF (Ser_Data='1') THEN   Int_Clk:=Int_Clk+1;  ELSE  Ticks_Count:=0;  Bit_Count:=0;   Cur_State <=Jump;   END IF;  ---------------------Skips the '31h' -------------------------------------------------------------   WHEN Jump=>   IF ( Bit_Count<10) THEN   Baud_Rate_Clk<='0';  IF (Ticks_Count < Int_Clk ) THEN   Ticks_Count:=Ticks_Count +1;  ELSE   Bit_Count:=Bit_Count+1;  Ticks_Count:=0;  END IF;  ELSE  Cur_state<= Next_Pkg;  END IF;  ---------------------Recives The Next Package And Test It ----------------------------------------   WHEN Next_Pkg=>   Baud_Rate_Clk<='0';  IF (Ser_Data='0') THEN   Cur_State<=Sample;  Bit_Count:=0;  Ticks_Count:=0;  Baud_Rate_Clk<='0';  END IF;  ---------------------Sample In The Middle Of the Bit ----------------------------------------   WHEN Sample=>  IF( Ticks_Count<(Int_Clk/2)) THEN   Ticks_Count:=Ticks_Count+1;   ELSE  Cur_state<=Output_Clk;  Bit_Count:=0;  Ticks_Count:=0;  Baud_Rate_Clk<='0';   Baud_Rate_Clk<='1';   END IF;  ---------------------Creating The New Clk for the Reciver Sample ----------------------------------------   WHEN Output_Clk=>  IF( Bit_Count<12) THEN   IF(Ticks_Count<Int_Clk) THEN   Ticks_Count:=Ticks_Count+1;   Baud_Rate_Clk<='0';   ELSE  Ticks_Count:=0;  Bit_Count:= Bit_Count+1;  Baud_Rate_Clk<='1';  END IF;  ELSE   Cur_state<=Next_Pkg;  Baud_Rate_Clk<='0';  END IF;  WHEN OTHERS=>NULL;  END CASE;   END IF; END PROCESS; END Baud_Rate_architecture;

[Altera_Forum]

(this one has more than 3 states , but also on 3 states it aint working ....)

[Altera_Forum]

--- Quote Start ---  (this one has more than 3 states , but also on 3 states it aint working ....)  --- Quote End ---     Hi,  I could open your statemachine with Quartus Web 7.0. I looks like that you found a bug in Quartus x.x. You should file a service request.  Kind regards  GPK

[Altera_Forum]

its aint working on the 9 addition ....really strange

[Altera_Forum]

Cr***y Quartus :D ... even version 9.1SP2, this thing still can't work properly.

[Altera_Forum]

--- Quote Start ---  Cr***y Quartus :D ... even version 9.1SP2, this thing still can't work properly.  --- Quote End ---     Hi,  did you file a service request ?   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  did you file a service request ?   Kind regards  GPK  --- Quote End ---    I will .... together with the "outdated processes" on the process panel :D Btw, I think Altera has a IP design team, they should've spotted these way earlier.  Nvm, I'll report.

[Altera_Forum]

i filled , still waiting for an answer...

[Altera_Forum]

Is there any new update to this? I have the same problem concerning my 85-state state machine.